搜索资源列表
dds_t
- 基于FPGA实现任意频率的DDS信号发生器-any frequence of DDS signal generate using FPGA
fre_pwm
- 可以调整频率和占空比的大小，用计数器来实现。时钟越高精度越好-FREQUENCE DUTY CYCLE
danpianji
- 单片机脉冲计数 基于51单片机实现对外来脉冲的计数功能 -FREQUENCE ACCOUNT
f020get_frequence
- 完整可以运行的基于F020的频率测量，非常精准了。-this is a program that used to get frequence basing on c8051f020.
DIV_FREQUENCY
- 此文件实现了简易的分频器功能。有一些误差，但有用武之处。-frequence divide
frequence
- 小学期做的频率计，功能是计算输入信号的频率-Primary frequency of doing design, function is to calculate the frequency of the input signal
frequence
- 用arm内核单片机stm32测量频率，该测量算法经过应用，达到理想要求-Microcontroller stm32 measurement frequency for
frequence
- VHDL语言频率计的设计，分为三个模块，计数模块和16位寄存器模块还有时序控制模块。-VHDL, the design of frequency meter
frequence
- 51单片机仿真实验，keil和proteus软件，数码管显示-51 MCU Experimental, keil and proteus software, digital display
CC2500Jump
- CC2500 frequence jump test ,it s ok that can transceive or receive
variation-de-la-frequence
- Programme pour la variation de la fréquence avec un PIC
Algo_Bco
- metaheuristique BCO pour probleme d affectation de frequence
R8C-M120A-frequence-METER
- 瑞萨R8C A120 做的频率计 硬件连接图与全套源码-Renesas R8C A120 to do the frequency counter and a full set of source hardware connection diagram
frequence
- 基于verilog语言的频率计，大三的时候写得，我感觉不错哦-Verilog language based on the frequency meter, junior, when written, I feel good, oh
20frequency-divider
- 20分频器的实现，利用Verilog语言-realize 20 frequence device by Verilog
fdivision_50Mto500K
- verilog 程序实现50M到500K的分频-verilog program to divion of frequence
SIN_NEW1Hz
- 正弦波信号的产生,频率为1Hz,FPGA处理模块各部分所需工作时钟信号由输入系统时钟信号经分频得到，系统时钟输入端应满足输入脉冲信号的要求-generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock
frequence-counter
- 簡單的計頻器設計很值得參考包括顯示uart clk led 1602 都在裡頭-Simple frequency counter design is worth considering include the display uart clk led 1602 are in the inside
electromagnetic-flowmeter
- 对消除电磁流量计信号中的工频干扰问题进行了分析和探讨。在理论上分析了不同的励磁频率、 采样点及宽度对测量精度的影响。经实际证明 ,利用理论分析的结果可以提高测量精度与加宽测量范围。-The question of 50 Hz power-line interference from electromagnetic flowmeter is discussed. Different exciting frequence , sampling spot and width are analyzed.
adder128x
- 128位加法器优化设计：64位加法运算+2-1多路选择器。并在关键路径上添加寄存器，降低延迟。 testbench可以测试优化的效果，在ISE中做过综合，能跑到200+MHz-128-bit adder optimization design: 64-bit adder+ 2-1MUX. In the key path, there are regs to improve the performance and reduce the delay time. you use the tes