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SDRAM_96M
- 基于FPGA的SDRAM串口实验,verilog语言写的,附件里是做实验的工程,连上串口,下进去就有数据了,波特率9600,一个停止位,SDRAM时钟是96MHz,数据时FPGA自动产生的,正确输出结果是00到FF递增一,再循环。这个工程警告比较少,基本是故意为之的警告,时序也已经收敛。-FPGA-based SDRAM serial experiments, verilog language written annex is to do the experiment works, even o
步进电机
- 控制步进电机正反转,采用C语言写的,STM32f103开发板系列(i do not tell you what this can do,so sorry!please yourself go to read then know what faction.)