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伪随机序列的说明和源代码
- 可控m序列产生器我分成四个小模块来做，M，M1，M2，M3分别对应为：m序列产生器、控制器、码长选择器、码速率选择器。-controllable m-sequence generator, I divided into four small modules do, M, M1, M2, M3, respectively : m-sequence generator, controller, code-selector, code rate selector.
mcode
- 一个典型的m序列发生器，生成m序列:1110010-a typical sequence generator m, m Sequence Generation : 1110010
mxuliematlab
- m序列在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-m sequence in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
fpdpsk
- FSK/PSK信号调制器的VHDL程序，共分为分频器、m序列产生器、跳变检测、2:1数据选择器、正弦波信号产生器和DAC(数、模变换器)6部分-FSK/PSK signal modulator VHDL program is divided into divider, m sequence generator, transition detection, 2:1 data selector, the sine wave signal generator and DAC (number, mode
Matlab-m-sequence-generator
- 介绍m序列和教你如何利用matlab进行编译m序列-Introduction of m-sequences and teach you how to use the matlab compiled m-sequence
M-sequence-generator
- M sequence generator using VHDL-M sequence generator
M
- 小M序列发生器。序列长度为7。方便修改。-Small M sequence generator. Sequence length is 7. Facilitate the change.
m
- m序列生成文件，带有我自己写的仿真，结果在modelsim6.0f中生成正确。-m sequence generation file, written with my own simulation results generated in the modelsim6.0f correct.
m_sequencer
- m序列发生器，长度可以变化，此处使用长度为40 的移位寄存器。反馈函数使用的是：x40+x5+x4+x3+1-m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
Verilog----m
- verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
FPGA-M-sequence-generator
- FPGA VHDL 语言M序列发生器，可以帮助各位需要的朋友探讨研究-FPGA VHDL language M-sequence generator, can you help a friend in need of research
m-xulie
- 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
M-sequence
- M序列具有伪随机特性，代码包含了M序列的生成和检测，可用于帧同步系统。-M-sequence has a pseudo-random properties, including the M-sequence code generation and detection, can be used for frame synchronization system.
M-sequence
- 编码器生成M序列进行通信，接收后再进行解码。用于扩频率通信中。通过状态机实现。-The encoder generates the M sequence for communication, the receiver and then decoded. For the expansion of the frequency communications. Through the state machine implementation.
M-series-digital-signal
- 第一路用于产生一个10Mbps的M序列，第二路产生10Kbps到100Kbps的M序列，数据率可以按10Kbps步进。-The first way to generate a sequence of M 10Mbps, the second way to produce 10Kbps to 100Kbps M-sequence data rate can 10Kbps steps.
m
- 这是vhdl编写的产生7位m序列的程序，类比可以产生更多为的。而m序列即可作为输入测试信号，也可以模拟噪声。-It is written vhdl 7 m sequence generation process, can produce more for the analogy. The m-sequence can be used as an input test signal, it can simulate noise.
m
- 本设计实现了一个12级m序列发生器，包含源文件及其测试文件。-This design has realized a level 12 m sequence generator, and the test file contains the source file.
m-sequence_gen
- m序列生成verilog代码，经过仿真测试，绝对可用，带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
m-Sequence
- FPGA,verilog,输出M序列，已调试成功，可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
E_2011
- 生成了一个M序列，适用于2011年全国电子设计竞赛的F题(A M sequence is generated that applies to the F question of the 2011 National Electronic Design Competition)