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mips_creative
- 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
mlite.tar
- Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
8bitRISCCPU
- 8bit RISC cpu 设计资料 包含夏宇闻老师的教程第8章-8bit RISC cpu design
MIPS_CPU
- 一个完整的MIPS CPU的设计，是创新设计项目，内含详细的项目设计报告-A complete MIPS CPU design, innovative design projects, detailed project design report containing
mipscpudesign
- cpu设计实例mips。MIPSI指令集32位CPU （1）MiniCore设计实例全32位操作，32个32位通用寄存器，所有指令和地址全为32位 （2）静态流水线（3～5级） （3）Forwarding技术 （4）片内L1 Cache，指令、数据各4KByte，硬件初始化 （5）没有TLB，但系统控制协处理器（CP0）具有除页面映射外的全部功能 -cpu design example mips. MIPSI instruction set 32-bit CPU (1)
IP_CORES
- IC内核的设计源码！其中包含MP3内核，CPU内核，I2C内核等多达式种IC设计的源码！-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
The_design_of_MIPS_CPU(VHDL)
- MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
mips1
- Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
CPU
- 多周期CPU设计，使用Verilog HDL语言编程，实现MIPS的指令系统。-CPU design with verilog hdl language.Instructions from MIPS.Something in detial is not perfect.
CPU
- mips系列，CPU的Verilog语言设计，自己写的-mips series, CPU of the Verilog language design, to write their own
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
mips-cpu
- 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
CPU
- 流水式CPU设计，实现在MIPS基础上修改的16位THCO-MIPS指令系统，解决了数据、结构、控制冲突，并实现了软硬中断-Pipelined CPU design, implementation, based on changes in the MIPS 16-bit THCO-MIPS instruction set to address the data structure, control of conflict, and to achieve the hard and soft int
MIPS-CPU
- 全指令集MIPS-CPU工程，包含各分模块工程、测试程序和详细设计文档，QuartusII7.2测试通过。-MIPS-CPU works full instruction set, contains the sub-module engineering, testing procedures and detailed design documents, QuartusII7.2, the test passes.
MIPS-and-CPU-design-and-simulation
- 兼容MIPS指令集的CPU设计与仿真 处理器架构为多周期，指令用32为字长（取指占一个周期），4k的存储器（指令存储器和数据存储器分开），IO与存储器统一编制，能支持20条指令以上-MIPS instruction set compatible CPU design and simulation
CPU
- 使用Verilog HDL语言完成一个简单的多周期MIPS微处理器的设计-Using Verilog HDL language to complete a simple multi-cycle MIPS microprocessor design
mips-cpu-master
- CPU设计，已通过模拟，有需要的自行下载吧(CPU design has been simulated)