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signal_cpu_sort
- Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_ME
mips_creative
- 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
mlite.tar
- Plasma IP Core 你可以利用这个组件在FPGA中设计MIPS结构的CPU -Plasma IP Core You can use this component in FPGA design the structure of MIPS CPU
mips3
- modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。
ucosii_bsp_jz-20070808
- mips cpu 君正4730 4740的 ucosii 源码 包括系统 摄像头 网络 文件系统等等测试
incaip
- 基于mips CPU，uboot下flash读与LCD显示程序。
disk
- 基于mips cpu,在u-boot系统下磁盘驱动程序。
MIPStest00
- 簡易MIPS CPU程式碼 此CPU包含 shift add sub and or stl beq lw sw 等功能
nandprog
- 君正MIPS CPU通用的boot loader源码，USB接口，学习nand flash编程和MIPS cpu 原理的好资料！通过nandprog将程序下载到君正的板子nand flash 里。-Jun MIPS CPU is a common source boot loader, USB interface, the learning nand flash programming and MIPS cpu principles of good information! By nandpro
ejtag-0.2
- mips e-jtag 加载uboot程序，实现直接控制cpu加载boot loader，无需事先烧写任何程序进flash-mips e-jtag loading uboot procedures to achieve direct control of the cpu load the boot loader, any program without prior programming into flash
Project4
- This zipfile is composed of a bunch of MIPS codes that might be helpful to some people who are developing CPU
pipeline
- 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
CU
- mips指令控制器。fpga上板验证实现。为cpu课设重要模块-mips instruction controller.
super_an218
- Using the 25 MIPS CPU and on-chip ADC, the C8051F300 can perform DTMF tone generation and decoding.
CPUsourcecode
- 本设计实现了一个具有标准的32位5级流水线架构的MIPS指令兼容CPU系统。具备常用的五十余条指令，解决了大部分数据相关，结构相关，乘除法的流水化处理等问题，并实现了可屏蔽的中断网络。-This design implements a standard 32-bit 5-stage pipeline architecture of MIPS instruction compatible CPU system. Instructions with more than 50 commonly use
mips
- cpu---risc---mips源代码-cpu---risc---mips
32mips-cpu
- 基于32为MIPS指令设计的cpu，32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
CPU
- 基于32位MIPS流水线CPU，由自己独立完成，-Pipelined 32-bit MIPS-based CPU, by themselves independently,
MIPS-CPU
- 完整的32位MIPS处理器工程，拥有整个工程和doc文件说明-Full 32-bit MIPS processor works with the entire project and doc file descr iption
mips-cpu-master
- CPU设计，已通过模拟，有需要的自行下载吧(CPU design has been simulated)