搜索资源列表
uboot1.1.6
- uboot 1.1.6源代码，支持ARM，MIPS，PowerPC等各种嵌入式CPU-uboot1.1.6 source code for ARM,MIPS,PowerPC and so on.
piplelinecpu
- 流水线CPU，实现MIPS简单指令的运行，在XLINX实验板上运行-Pipelined CPU, MIPS simple instructions to achieve the operation, run in XLINX experimental board
PipelineCPU
- 设计一个32位流水线MIPS微处理器，具体要求如下： 1. 至少运行下列MIPS32指令。 ①算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。 ②逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。 ③移位指令：SLL、SLLV、SRL、SRLV、SRA。 ④条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。 ⑤无条件跳转指令：J、JR。 ⑥数据传送指令：LW、SW
muCPU_final
- 用Verilog开发的多周期CPU,可执行mips汇编中的R\I\J型指令，具有较高的参考价值。-Using Verilog development of multi-cycle CPU, mips executable compilation of R \ I \ J-type instruction, with a high reference value.
MIPSCPU
- 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
Our_MIPS_CPU
- 基于MIPS架构的CPU设计，含有完整程序代码，及各模块实现及仿真程序！-CPU design based on MIPS architecture, contains a complete code, and the realization of each module and the simulation program
Project3-Logisim
- 用logisim写的单周期CPU，可以跑MIPS汇编编译的二进制代码，测试完美通过，供学弟学妹参考，计算机组成原理试验-Logisim write cycle with a single CPU, you can run the MIPS assembler binary code, test perfect pass for mentees reference, computer composition principle test
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
PipelineCPU
- 一个用Verilog HDL语言所写的32位MIPS指令系统流水线CPU，含代码工程文件和相关设计说明文档，比较详细。-verilog HDL, 32 MIPS pipeline CPU
soc_sram_func
- 利用verilog编写的32位 MIPS指令集CPU，sram接口，已上板验证(The 32 bit MIPS instruction set CPU, SRAM interface written by Verilog has been verified on board.)