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文件包为浮点快速傅立叶变换（32点）的汇编代码，运行在ADI的Visual DSP++平台上，由于结合了并行流水线指令，该算法具有很高的运行效率，可以被广泛使用在高速数字信号处理方面。-package for floating-point fast Fourier transform (32 points) compiled code, ADI operations in the Visual DSP platform, thanks to a combination of a parallel
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For developers using FPGAs for the
implementation of floating-point DSP
functions, one key challenge is how to
decompose the computation algorithm
into sequences of parallel hardware
processes while efficiently managing data flow through th
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这个是我花了一个星期的CRC算法，有并行与串行的区别与时序的分析。。。。希望站长能够同意-This is a week I spent the CRC algorithm, there is the difference between parallel and serial and timing analysis. . . . Hope that regulators can not agree
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cannon 并行程序
Matrix multiplication with the Cannon Algorithm:
The matrices A and B are stored in files. The file names have to be specified as parameter. The root
process reads the matrices and distributes the respective values to all processes,
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潘明海 刘英哲 于维双 (论文)
中文摘要：
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Mingha
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探讨用于直接序列扩频的数字匹配滤波器(DM )的逻辑结构和有关参敷的选取问题；
讨论了采用并行处理技术和快速算法的可行性，分析了量化比特数、取样间隔以及A／D变换器固有的
软限幅鼓应对系统性能的影响；为有所比较，还提到了早期的柱性重合D^ 。在给出部分理论分析和计
算机模拟结果之后归纳了几条主要结论，这叶在目前国内条件下设计DⅦ 特别具有参考价值。-Explore for direct sequence spread spectrum digital matched filter (
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采用Cyclone EP1C3，VHDL程序算法实现了信号波形的实时采样并回放，同时能测量时域信号的频率，通过与MCU的8位并行接口，进行相互通信。-Using Cyclone EP1C3, VHDL program algorithm of the signal waveform of real-time sampling and playback at the same time capable of measuring the frequency of the signal in time
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通过TMS320C6X系列DSP芯片实现平行束卷积的投影算法，并给出原理框图，完成了CT图像重建，-TMS320C6X series DSP chip through parallel beam convolution of the projection algorithm of block diagram, completed the CT image reconstruction,
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人工神经网络（ArtificialNeuralNetworks，简写为ANNs）也简称为神经网络（NNs）或称作连接模型（ConnectionistModel），它是一种模范动物神经网络行为特征，进行分布式并行信息处理的算法数学模型。这种网络依靠系统的复杂程度，通过调整内部大量节点之间相互连接的关系，从而达到处理信息的目的。
-Artificial neural network (ArtificialNeuralNetworks, abbreviated as ANNs) also refe
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64位数据的CRC-32校验的，Verilog实现，算法并行优化-64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm
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用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
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Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
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Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
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Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
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给大家介绍关于crc校验原理和算法。并在fpga实现描述。-To introduce the crc check principle and algorithm。To achieve the descr iption in fpga
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32位数据输入并行算法Verilog HDL代码。-32 bits of data input and parallel algorithm Verilog HDL code
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实现FIR滤波器的并行算法，这里是一个64阶的低通滤波器-FIR filter of parallel algorithm
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串行转并行算法，自己编写，已经运行成功，算法简单易懂。-Serial to parallel algorithm
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采用并行算法实现流水灯设计,其中top_module是顶层文件。-Flash light by parallel algorithm design
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BT1120格式的NRZI编码,并行算法-NRZI encoding BT1120 format, parallel algorithm
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