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这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communicatio
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并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用,String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
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串行输入并行输出 用vhdl语言描述的 有源代码主打色,Serial input parallel output using vhdl language to describe the main color of the source code
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8.1 可编程并行接口芯片8255A
8.2 可编程定时器/计数器芯片8253/8254
8.3 串行通信及可编程串行接口芯片8251A
8.4 模/数（A/D）与数模（D/A）转换技术
及其接口
-8.1 programmable parallel interface chip 8255A8.2 programmable timer/counter chip 8253/82548.3 serial communications and programmable seri
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基于ISD4004的语音报值交直流电压表的设计：本文介绍了基于语音芯片ISD4004的语音报值交直流电压表的设计。电路由数据采集部分，A/D转换部分，键盘与显示部分，单片机控制部分，语音报值部分和扩展功能部分组成。电路使用了并行与串行总线相结合的方式，使设计与编程灵活简便。创意新颖有趣，富于人性化，避免了频繁观察仪器显示之苦，对减轻工程技术人员的工作量和提高工作效率现实意义。-ISD4004 voice-based value of AC and DC voltage at the design
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本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
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This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
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parallel to serial data converter using VHDL
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this code is designed to perform parallel to serial operation it is very essential in every design
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this code is designed to perform serial to parallel it is essential to every design
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这是一个将6组并行数据串行输出的VHDL源码，配合外部电路可以输出正负脉冲，还附有逻辑图哦。-This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
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基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE softwa
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文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
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its code for converting serial to parallel processing data
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vhdl code to change the bits stream from parallel to serial
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包含16位CRC的并行实现和串行实现，并有测试程序。-Includes 16-bit CRC of the parallel and serial implementation to achieve, and test procedures.
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用软件实现CRC校验码计算很难满足高速数据通信的要求， 基于硬件的实现方法中， 有串行经典算法LFSR,电路以及由软件算法推导出来的其它各种并行计算方法。以经典的LFSR,电路为基础， 研究了按字节并行计算CRC校验码的原理.-Implemented in software CRC checksum calculation is difficult to meet the requirements of high-speed data communications, hardware-based
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ad9910 DDS板 VHDL源代码，在Cyclone II FPGA上调试通过，主要文件说明：
Filename Function
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dds_controller.vhd top entity, opcode decoding
ddslib.vhd configuration,opcode definition
dds_serial.vhd parallel to s
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VHDL写的串并转换代码，经ISE13.3测试能用的。-VHDL to write a serial-to-parallel conversion code, can be used the ISE13.3 test.
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SERIAL TO PARALLEL VHDL CODE
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