datapath code in verilog for pipeline processor

MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - reg

datapath of 8bit synthesized risc processor

pipelined datapath for MIPS Processor full project