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rtl
- 用verilog编写的网卡芯片rtl级。前仿后仿都通过了，可以在modelsim上运行察看-verilogrtl After the former imitation through imitation, it can run on the look modelsim
RTL-lwIP-0.6
- RTL-lwIP is the porting of the lwIP TCP/IP stack to RTLinux-GPL.The focus of the RTL-lwIP stack is to reduce memory usage and code size, making RTL-lwIP suitable for use in small clients with very limited resources such as embedded systems. -RT
c8051
- USB v1.1 RTL and design specification
lpc2148_usb
- ARM] KEIL RTL-USB FOR LPC2148 的3个USB例子的阅读笔记_ ARM] KEIL RTL-USB FOR LPC2148 的3个USB例子的阅读笔记_-ARM] KEIL RTL-USB FOR LPC2148 examples of the three reading USB Notebook _ARM] KEIL RTL-USB FOR LPC2148 examples of the three reading USB Notebook _ARM] KEIL RT
aes_verilog
- A RTL verilog coding for the project AES, which is a cryptography based concepts
RTL
- The RTL-ARM User s Guide contains detailed information about the components of the RTL-ARM Real-Time Library
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
rtl
- 液晶model 设计LCD 并口模式下的仿真model-LCD FIFO model
xapp851
- The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - Synthesis related files \par - Place/Route related files-The xapp
i2c
- i2c rtl code , document, simulation
spi
- SPI总线的RTL源代码，很好用，省掉你大量的工作量-the spi bus RTL Code
singt
- 用VHDL语言描述的用锁存器，加法计数器，ROM存储器构成的RTL图-VHDL language used to describe the use of latches, adding counters, ROM memory map consisting of RTL
fft_rtl
- rtl实现的fft变换，经硬件测试其功能与altera的fftip核相近-fft transform based on rtl design
lab04
- RTL in Verilog (Vending Machine)
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
watch_dog_rtl_source
- Watchdog timer verilog RTL code
Describing-Synthesizable-RTL-in-SystemC
- Describing Synthesizable RTL in SystemC
Wiley.IEEE.Press.RTL.Hardware.Design.Using.VHDL.A
- Wiley IEEE PRESS RTL Hardware Design using VHDL 2006
Principles-of-Verifiable-RTL-Design
- RTL设计的基本方法，帮助掌握RTL编码方法-RTL