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Verilog-statemachine
- 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
statemachine
- 自己做的一个关于more状态机的三种描述的比较。以后会有更多的资料，请大家关注。-doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
statemachine
- 状态机是FPGA系统工程应用中应用较多的工具 能有效实现系统的逻辑功能
statemachine
- 硬件描述语言的例程，开发板上的例程，大家看看吧。
111
- statemachine it can detecate statemachine
mcu_RTOS_task
- DIY自己的单片机多任务系统。stateMachine+timerTick+q
statemachine
- 用VHDL实现的有限状态机，还有modelsim仿真文件，及仿真结果-VHDL implementation using finite state machine, there modelsim simulation file, and the simulation results
StateMachine
- 典型的状态机，简单的状态机可以不需要编码，也可以采用one-hot编码方式，如果状态很多时，采用格雷码，能有效避免亚稳态。-A typical state machine, a simple state machine can do without coding, can also be used one-hot encoding, if the state in many cases, the use of Gray code, can effectively avoid metastable
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
StateMachine-based
- FPGA上的利用状态机实现的分频的verilog程序-verilog source code StateMachine-based for FPGA
statemachine
- An example of state machines
statemachine
- 一个用vhdl语言写的交通灯控制的例子，可以很好的学习vhdl语言中状态机的使用。-Written in a language with vhdl traffic light control case study can be a good vhdl state machine language to use.
statemachine
- 状态机可以实现几个状态之间的转换,这时使用qt编写的verilog文件-statemachine for inter change between any one of them
TAP1
- JTAG TAP statemachine verilog code
TAP2
- JTAG TAP Statemachine verilog code
TAP3
- JTAG TAP Statemachine verilog code
TAP4
- JTAG TAP Statemachine verilog code
statemachine
- 使用有限状态机的概念实现小型仪器多机通信协议，具有很高的稳定性与可靠性。-The concept of finite state machines using a small instrument to achieve multi-machine communication protocol, with high stability and reliability.
statemachine
- RTL级verilog代码 用状态机实现 将输入数据写入16位寄存器，输出其除以7所得的余数（4位）-RTL-lever verilog code Using FSM to realize the following function:input the data into a 16bit register, divide it by 7, and output the 4-bit remainder