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viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
nonsystem
- Generate trellis data of a rate-1/n convolutional encoder.卷积码1/n的编码器，注意生成的是非系统码。-Generate trellis data of a rate-1/n convolutional encoder. Convolutional codes 1/n of the encoder, the attention generated by the non-system code.
misc-dspdomain
- DSP RELATED STUFF related to constellations and Trellis coded modulation.
98_1099
- Viterbi, Trellis and Turbo Code implementation on a next-generation DSP
Viterbi_check
- It is a verilog code for viterbi decoding with trellis diagram
TCM
- Trellis coded modulation(TCM) VHDL code
RAM_BLOCK
- Ram block code in Verilog
lcd_test2.tar
- 在6410開發板上,framebuffer上畫上格子圖-In 6410 development board, framebuffer painted on a trellis diagram
1
- DNA Cryptography and Trellis Algorithm
Ranjan Paper_I
- Essentially, two different space-time coding methods, namely space-time trellis codes (STTCs) and space-time block codes (STBCs) have been proposed. STTC has been introduced in [3] as a coding