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VHDL_language_design_of_CRC_incidence_and_validato
- VHDL语言设计的CRC发生和校验器VHDL language design of CRC incidence and validator-VHDL language design of CRC incidence and validator VHDL language design of CRC incidence and validator
sequential-detactor
- 本次例程包括七阶伪随机序列发生器、序列码检测器，奇偶校验器、CRC（循环冗余）校验器，并附有FPGA的代码和仿真。-The routines including seven order pseudo-random sequence generator, sequence yards detector, parity validator, CRC (cyclic redundancy) validator, and with FPGA code and simulation.
hibernate_validator
- Hibernate Validator Reference Guide Hibernate Validator works at two levels. First, it is able to check in-memory instances of a class for constraint violations. Second, it can apply the constraints to the Hibernate metamodel and incorporate
conv
- 用汇编语言编写卷积运算。Visual DSP++软件环境下使用三角波和正弦波卷积运算验证程序，与MATLAB仿真结果对比。 -Convolution written in assembly language. Visual DSP++ using the triangle wave and sine convolution validator software environment, compared with the MATLAB simulation results.
jiaoshi
- 基于单片机的含有校时功能的时钟程序，已经验证器正确性-Contains a microcontroller-based school program when the clock function has validator correctness