搜索资源列表
FPGAMP3_LUKA_Project_Proposal
- The goal of this project is to design a MPEG Layer III (MP3) player using a FPGA board. The FPGA will read MP3 source files, decode them into a 16-bit Pulse Code Modulated (PCM) output, and play the audio files through an external speaker.
uart_transceiver
- 一个通用串口通信FPGA程序。大家可以借鉴-a uart FPGA pragram.you can modify and use it in your project.
RS_232
- VHDL实现RS232串口通信，压缩包内有完整的quartus2工程，由顶层，波特率，发送，接收四个模块构成。外部电路只需要一片MAX232就能与串口助手或单片机通信。-VHDL implementation of RS232 serial communication, compressed within a complete quartus2 project from the top, baud rate, send, receive four modules. External circui
VHDL100
- VHDL的工程100道实例，内容比较好，适合初学者，上课老师的讲稿，通俗易懂！给大家分享下-Examples of VHDL project 100, the content is better for beginners, school speech teacher, easy to understand! To share with you
Project-Clock-plus-alarm
- 实现超多功能数字钟的vhdl硬件实现，可以实现校时校分闹铃，多模切换，多模同时工作-Ultra-versatile digital clock vhdl hardware implementation can be achieved when the school hours the school alarm, multi-mode switching, multi-mode simultaneously
de2_70_air_hockey_game
- Verilog/VHDL project that implements a Air-Hockey game using a DE2-70 board and a LTM touch panel.
uart-
- 通用异步通讯UART的工程文档，ISE打开工程，里面有VERILOG的源代码，可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
LCD-display
- fpga的键盘阵列LCD显示程序，包括vhdl文件，顶层文件和工程文件-fpga array of keyboard LCD display procedures, including vhdl files, top-level files and project files
ADSP2011Local
- pci9054芯片本地总线控制示例程序，可用于pci驱动和应用程序的测试。每隔一段时间产生一次中断，产生1，2，3等递增数据，配合pci9054驱动和应用程序完成数据传输 2.说明：文件夹内是Quartus 9.0的工程文件，使用Verilog语言。-pci9054 local bus control chip sample program can be used for pci driver and application testing. Generate an interrupt at r
VHDL-Project
- Design of a Moore Synchronous Sequential Machine that operates according to the following two sequences.
adfmreceiver
- The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia p
working_code
- rs 485 working code for project
vhdl
- 基于vhdl的串行扫描显示电路设计，打开工程文件就可实现，并提供下载文件。-Vhdl serial scan based circuit design, open the project file can be achieved and provides download the file.
project
- It provides the code of or and decoder24 and encoder42 in VHDL language
VHDL
- 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
Verilog-Niosii-TLC1549
- niosii的一个完整的工程 Q2 软件是9.1版本，里面做了一个TLC1549的AD转换串转并的模块-niosii project with a TLC1549 module
TrafficLight
- VHDL开发的数字交通灯控制器，项目实训内容；-The development of digital traffic light controller VHDL, project training content
dc3and8
- 3-8译码器VHDL工程源代码，含工程、VHDL源码、下载文件等-3-8 decoder VHDL project sourcecode
counter
- this source is a counter vhdl project :)
ProjectLoto
- VHDL Project for a loto application