用VHDL语言设计维特比 解码器 是VHDL原代码用ModelSim XE III 6.3c软件实现仿真-Language Design with VHDL Viterbi decoder is the VHDL source code with ModelSim XE III 6.3c software simulation

Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog

viterbi decoder with convolutional encoder