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bist 2017 paper
- A new low-power (LP) scan-based built-in selftest (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding. A new LP scan architecture is proposed, which supports both pseudorandom testing and deterministi
Coding Files
- Through this paper our attempt is to give a onetime networking solution by the means of merging the VLSI field with the networking field as now a days the router is the key player in networking domain so the focus remains on that itself to get a good
VLSI_IEEE_2016_List
- VHDL IEEE 2016,2017 Project List
add.v
- 这是verilog的加法器。它可用于超大规模集成电路设计。(This is an adder by Verilog. It can be used for VLSI design.)
LDPC码编译码算法的研究与实现_陈石平
- 本文首先回顾了LDPC码的发展历程和现状，介绍了LDPC码检验矩阵的构造、编 译码原理。在对编译码作了深入探讨和分析后，接着进行了RU算法编码和长码编码 的FPGA实现;根据二叉树的性质，提出了一种长码编码的ASIC优化设计的方法，节省 了大量硬件资源;论文详细阐述了CORDIC算法原理以及LDPC码译码中所采用的指 数函数和反双曲正切函数的FPGA实现:CORDIC内核及前后处理单元设计、仿真、综 合及数据分析，这对LDPC码的译码具有很重要的意义，为用数字VLSI来实现LDPC的
DLL_clock_generator
- DLL is useful for the ug and pg sdents tu
VLSI verilog
- booth multiplier using booth algorithm
formal_verification
- 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)