搜索资源列表
Modelsim_Xilinx_Simulation_library_compile
- Modelsim中Xilinx仿真库的编译方法-The compile method for xilinx simulation library in Modelsim
serial_communication
- 使用Xilinx公司的FPGA，采用Verilog HDL语言实现串口数据的发送与接收。-Using Xilinx' s FPGA, Verilog HDL language used to send and receive serial data.
ps2_key_dds_50M
- 利用xilinx开发板，使用嵌入式系统，编写的ps2键盘和利用dds原理产生正弦波的程序-Using xilinx development board, the use of embedded systems, the preparation of the ps2 keyboard and use the procedures dds elements of the sine wave
lab3_adding_ip
- xilinx embeded添加ip的源程序,包括工程文件-xilinx embeded adding ip
sp601_BIST_rdf0045_12.2
- xilinx sp601开发板自检程序，可以帮助初学者对sp601开发板的学习-xilinx sp601 development board self-test program that can help beginners learn on the sp601 Development Board
frequency
- 基于XILINX平台设计的数字频率计，在FPGA内部设计信号源，产生100KHz方波，板上数码管用于显示被测信号频率，并显示6位有效数字，实现对TTL电平的测试，测量精度为10Hz。-: The digital frequency meter based on XILINX development terrace generates 100 KHz square waves by a supply oscillator within FPGA. The nixietubes of the boa
user-guide
- xilinx用户指南for ML505/ML506/ML507-User Guide
ModelsimVHDLWatch
- This tutorial is a part of a series of tutorials provided by Xilinx to lead the user through the Xilinx FPGA Design Flow. This archive contains the necessary design files to perform the tutorial.-This tutorial is a part of a series of tutorials p
12864_4_done
- xilinx fpga 中嵌入MicroBlaze软核处理器 实现12864液晶的控制 显示字符 汉字 自定义字符 图片 任意绘图-xilinx fpga MicroBlaze embedded soft core processor to control the liquid crystal display 12864 characters in any Chinese custom character drawing pictures
ModelsimVerilogWatch
- Stopwatch Design - ModelSim Vlog Tutorial Required Software: - Model Technology Modelsim 5.4a - Xilinx Development System 3.1i CONTROLS Inputs: * CLK -System clock for the Watch design. * STRTSTOP -Starts and stops the stoopwatch
IS61WV51216BLL
- 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher M
gj-2s
- 基于赛灵思EXCD-1的FPGA开发板，使用ISE10.1开发环境，使用VHDL语言编写，功能为计算输入方波的频率。输入方波，输出方波的频率，用数码管显示，每2s更新一次。管脚配置见工程。-Based on the FPGA Xilinx EXCD-1 development board, using ISE10.1 development environment, using the VHDL language, functions for calculating the frequency
FPGAspwm
- 在Xilinx公司的Spartan ⅡE系列的XC2S100E pq-208 FPGA芯片上完成PWM波和SPWM波控制信号，控制电力电子器件IGBT和MOSFET构成的斩波、逆变输出电路，实现直流稳压和SPWM交流调频输出。-In Xilinx' s Spartan Ⅱ E Series XC2S100E pq-208 FPGA chip to complete SPWM wave PWM control signal wave and control the power electro
QAM16_demo
- This a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery. -This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xil
XilinxFPGA(1-60)
- 系统地讲述了Xilinx FPGA的开发知识，包括FPGA开发简介，Verilog HDL语言基础、基于Xilinx芯片的HDL语言高级进阶、ISEd开发环境使用指南等-Systematically describes the development of Xilinx FPGA knowledge, including Introduction to FPGA development, Verilog HDL language based on chip-based Xilinx HDL La
OFDM_Security
- This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA. The RAR file inlcudes 2 files: 1. Simul
cadsp
- 运用xilinx FPGA实现一幅图片的二值化，彩色图片变为灰度图片-Using xilinx FPGA realizing a picture of binary, color images into grayscale images
Erosion1
- 运用FPGA xilinx的system gennerator对图片进行腐蚀-Using the system gennerator FPGA xilinx corrosion images
Falcon_E25GT_Plugin
- 用于xilinx FPGA芯片的DSP功能的一些例子，在世闻开发板E25GT上验证通过。-DSP chips for xilinx FPGA features some of the examples on earth smell development board E25GT verified.
perjoko_ting_ting
- Simple Microprocessor built with XILINX ISE