此代码可用modelsim进行仿真，修改rom之后可用quartusII进行综合，希望你们能对此程序不断完善。-modelsim this code can be used for simulation, After amending rom available quartusII comprehensive and hope that you can constantly improve this procedure.

16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code

使用verilog代码描述了一种简单的单周期MIPS处理器实现，并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.

微处理器设计（verilog）带测试验证代码modelsim仿真无误 -Microprocessor design (verilog) with modelsim simulation test verification code is correct