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文件名称:SCMIPS
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- 上传时间:2012-11-16
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文件大小:131.45kb
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已下载:0次
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介绍说明--下载内容来自于网络,使用问题请自行百度
使用verilog代码描述了一种简单的单周期MIPS处理器实现,并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SCMIPS/
SCMIPS/memfile.dat
SCMIPS/SCMIPS.cr.mti
SCMIPS/SCMIPS.mpf
SCMIPS/SCMIPS.v
SCMIPS/SCMIPS.v.bak
SCMIPS/testdata/
SCMIPS/testdata/memfile.dat
SCMIPS/testdata/mipstest.asm
SCMIPS/vsim.wlf
SCMIPS/work/
SCMIPS/work/adder/
SCMIPS/work/adder/verilog.asm
SCMIPS/work/adder/verilog.rw
SCMIPS/work/adder/_primary.dat
SCMIPS/work/adder/_primary.dbs
SCMIPS/work/adder/_primary.vhd
SCMIPS/work/alu/
SCMIPS/work/aludec/
SCMIPS/work/aludec/verilog.asm
SCMIPS/work/aludec/verilog.rw
SCMIPS/work/aludec/_primary.dat
SCMIPS/work/aludec/_primary.dbs
SCMIPS/work/aludec/_primary.vhd
SCMIPS/work/alu/verilog.asm
SCMIPS/work/alu/verilog.rw
SCMIPS/work/alu/_primary.dat
SCMIPS/work/alu/_primary.dbs
SCMIPS/work/alu/_primary.vhd
SCMIPS/work/controller/
SCMIPS/work/controller/verilog.asm
SCMIPS/work/controller/verilog.rw
SCMIPS/work/controller/_primary.dat
SCMIPS/work/controller/_primary.dbs
SCMIPS/work/controller/_primary.vhd
SCMIPS/work/datapath/
SCMIPS/work/datapath/verilog.asm
SCMIPS/work/datapath/verilog.rw
SCMIPS/work/datapath/_primary.dat
SCMIPS/work/datapath/_primary.dbs
SCMIPS/work/datapath/_primary.vhd
SCMIPS/work/dmem/
SCMIPS/work/dmem/verilog.asm
SCMIPS/work/dmem/verilog.rw
SCMIPS/work/dmem/_primary.dat
SCMIPS/work/dmem/_primary.dbs
SCMIPS/work/dmem/_primary.vhd
SCMIPS/work/flopr/
SCMIPS/work/flopr/verilog.asm
SCMIPS/work/flopr/verilog.rw
SCMIPS/work/flopr/_primary.dat
SCMIPS/work/flopr/_primary.dbs
SCMIPS/work/flopr/_primary.vhd
SCMIPS/work/imem/
SCMIPS/work/imem/verilog.asm
SCMIPS/work/imem/verilog.rw
SCMIPS/work/imem/_primary.dat
SCMIPS/work/imem/_primary.dbs
SCMIPS/work/imem/_primary.vhd
SCMIPS/work/maindec/
SCMIPS/work/maindec/verilog.asm
SCMIPS/work/maindec/verilog.rw
SCMIPS/work/maindec/_primary.dat
SCMIPS/work/maindec/_primary.dbs
SCMIPS/work/maindec/_primary.vhd
SCMIPS/work/mips/
SCMIPS/work/mips/verilog.asm
SCMIPS/work/mips/verilog.rw
SCMIPS/work/mips/_primary.dat
SCMIPS/work/mips/_primary.dbs
SCMIPS/work/mips/_primary.vhd
SCMIPS/work/mux2/
SCMIPS/work/mux2/verilog.asm
SCMIPS/work/mux2/verilog.rw
SCMIPS/work/mux2/_primary.dat
SCMIPS/work/mux2/_primary.dbs
SCMIPS/work/mux2/_primary.vhd
SCMIPS/work/regfile/
SCMIPS/work/regfile/verilog.asm
SCMIPS/work/regfile/verilog.rw
SCMIPS/work/regfile/_primary.dat
SCMIPS/work/regfile/_primary.dbs
SCMIPS/work/regfile/_primary.vhd
SCMIPS/work/signext/
SCMIPS/work/signext/verilog.asm
SCMIPS/work/signext/verilog.rw
SCMIPS/work/signext/_primary.dat
SCMIPS/work/signext/_primary.dbs
SCMIPS/work/signext/_primary.vhd
SCMIPS/work/sl2/
SCMIPS/work/sl2/verilog.asm
SCMIPS/work/sl2/verilog.rw
SCMIPS/work/sl2/_primary.dat
SCMIPS/work/sl2/_primary.dbs
SCMIPS/work/sl2/_primary.vhd
SCMIPS/work/testbench/
SCMIPS/work/testbench/verilog.asm
SCMIPS/work/testbench/verilog.rw
SCMIPS/work/testbench/_primary.dat
SCMIPS/work/testbench/_primary.dbs
SCMIPS/work/testbench/_primary.vhd
SCMIPS/work/top/
SCMIPS/work/top/verilog.asm
SCMIPS/work/top/verilog.rw
SCMIPS/work/top/_primary.dat
SCMIPS/work/top/_primary.dbs
SCMIPS/work/top/_primary.vhd
SCMIPS/work/_info
SCMIPS/work/_temp/
SCMIPS/work/_temp/vlog0qmakf
SCMIPS/work/_temp/vlog10akxw
SCMIPS/work/_temp/vlog2mtkxb
SCMIPS/work/_temp/vlog3191hx
SCMIPS/work/_temp/vlog4nqmqm
SCMIPS/work/_temp/vlog8f0r8v
SCMIPS/work/_temp/vlog8hc6nw
SCMIPS/work/_temp/vlogacrrv3
SCMIPS/work/_temp/vlogatxwf6
SCMIPS/work/_temp/vlogcict71
SCMIPS/work/_temp/vlogdhgxse
SCMIPS/work/_temp/vlogeg7z8q
SCMIPS/work/_temp/vlogj3g49v
SCMIPS/work/_temp/vlogjssjt9
SCMIPS/work/_temp/vlogk0tfea
SCMIPS/work/_temp/vlogkdfm3q
SCMIPS/work/_temp/vlogrhs0md
SCMIPS/work/_temp/vlogrrz5kx
SCMIPS/work/_temp/vlogs1dw87
SCMIPS/work/_temp/vlogs7gj5k
SCMIPS/work/_temp/vlogscgtns
SCMIPS/work/_temp/vlogsqi3sm
SCMIPS/work/_temp/vlogvrvh57
SCMIPS/work/_temp/vlogxsssd2
SCMIPS/work/_temp/vlogxx0436
SCMIPS/work/_temp/vlogzqi69y
SCMIPS/work/_temp/vlogzs4jm2
SCMIPS/work/_vmake
SCMIPS/控制台显示.png
SCMIPS/测试结果.png
SCMIPS/memfile.dat
SCMIPS/SCMIPS.cr.mti
SCMIPS/SCMIPS.mpf
SCMIPS/SCMIPS.v
SCMIPS/SCMIPS.v.bak
SCMIPS/testdata/
SCMIPS/testdata/memfile.dat
SCMIPS/testdata/mipstest.asm
SCMIPS/vsim.wlf
SCMIPS/work/
SCMIPS/work/adder/
SCMIPS/work/adder/verilog.asm
SCMIPS/work/adder/verilog.rw
SCMIPS/work/adder/_primary.dat
SCMIPS/work/adder/_primary.dbs
SCMIPS/work/adder/_primary.vhd
SCMIPS/work/alu/
SCMIPS/work/aludec/
SCMIPS/work/aludec/verilog.asm
SCMIPS/work/aludec/verilog.rw
SCMIPS/work/aludec/_primary.dat
SCMIPS/work/aludec/_primary.dbs
SCMIPS/work/aludec/_primary.vhd
SCMIPS/work/alu/verilog.asm
SCMIPS/work/alu/verilog.rw
SCMIPS/work/alu/_primary.dat
SCMIPS/work/alu/_primary.dbs
SCMIPS/work/alu/_primary.vhd
SCMIPS/work/controller/
SCMIPS/work/controller/verilog.asm
SCMIPS/work/controller/verilog.rw
SCMIPS/work/controller/_primary.dat
SCMIPS/work/controller/_primary.dbs
SCMIPS/work/controller/_primary.vhd
SCMIPS/work/datapath/
SCMIPS/work/datapath/verilog.asm
SCMIPS/work/datapath/verilog.rw
SCMIPS/work/datapath/_primary.dat
SCMIPS/work/datapath/_primary.dbs
SCMIPS/work/datapath/_primary.vhd
SCMIPS/work/dmem/
SCMIPS/work/dmem/verilog.asm
SCMIPS/work/dmem/verilog.rw
SCMIPS/work/dmem/_primary.dat
SCMIPS/work/dmem/_primary.dbs
SCMIPS/work/dmem/_primary.vhd
SCMIPS/work/flopr/
SCMIPS/work/flopr/verilog.asm
SCMIPS/work/flopr/verilog.rw
SCMIPS/work/flopr/_primary.dat
SCMIPS/work/flopr/_primary.dbs
SCMIPS/work/flopr/_primary.vhd
SCMIPS/work/imem/
SCMIPS/work/imem/verilog.asm
SCMIPS/work/imem/verilog.rw
SCMIPS/work/imem/_primary.dat
SCMIPS/work/imem/_primary.dbs
SCMIPS/work/imem/_primary.vhd
SCMIPS/work/maindec/
SCMIPS/work/maindec/verilog.asm
SCMIPS/work/maindec/verilog.rw
SCMIPS/work/maindec/_primary.dat
SCMIPS/work/maindec/_primary.dbs
SCMIPS/work/maindec/_primary.vhd
SCMIPS/work/mips/
SCMIPS/work/mips/verilog.asm
SCMIPS/work/mips/verilog.rw
SCMIPS/work/mips/_primary.dat
SCMIPS/work/mips/_primary.dbs
SCMIPS/work/mips/_primary.vhd
SCMIPS/work/mux2/
SCMIPS/work/mux2/verilog.asm
SCMIPS/work/mux2/verilog.rw
SCMIPS/work/mux2/_primary.dat
SCMIPS/work/mux2/_primary.dbs
SCMIPS/work/mux2/_primary.vhd
SCMIPS/work/regfile/
SCMIPS/work/regfile/verilog.asm
SCMIPS/work/regfile/verilog.rw
SCMIPS/work/regfile/_primary.dat
SCMIPS/work/regfile/_primary.dbs
SCMIPS/work/regfile/_primary.vhd
SCMIPS/work/signext/
SCMIPS/work/signext/verilog.asm
SCMIPS/work/signext/verilog.rw
SCMIPS/work/signext/_primary.dat
SCMIPS/work/signext/_primary.dbs
SCMIPS/work/signext/_primary.vhd
SCMIPS/work/sl2/
SCMIPS/work/sl2/verilog.asm
SCMIPS/work/sl2/verilog.rw
SCMIPS/work/sl2/_primary.dat
SCMIPS/work/sl2/_primary.dbs
SCMIPS/work/sl2/_primary.vhd
SCMIPS/work/testbench/
SCMIPS/work/testbench/verilog.asm
SCMIPS/work/testbench/verilog.rw
SCMIPS/work/testbench/_primary.dat
SCMIPS/work/testbench/_primary.dbs
SCMIPS/work/testbench/_primary.vhd
SCMIPS/work/top/
SCMIPS/work/top/verilog.asm
SCMIPS/work/top/verilog.rw
SCMIPS/work/top/_primary.dat
SCMIPS/work/top/_primary.dbs
SCMIPS/work/top/_primary.vhd
SCMIPS/work/_info
SCMIPS/work/_temp/
SCMIPS/work/_temp/vlog0qmakf
SCMIPS/work/_temp/vlog10akxw
SCMIPS/work/_temp/vlog2mtkxb
SCMIPS/work/_temp/vlog3191hx
SCMIPS/work/_temp/vlog4nqmqm
SCMIPS/work/_temp/vlog8f0r8v
SCMIPS/work/_temp/vlog8hc6nw
SCMIPS/work/_temp/vlogacrrv3
SCMIPS/work/_temp/vlogatxwf6
SCMIPS/work/_temp/vlogcict71
SCMIPS/work/_temp/vlogdhgxse
SCMIPS/work/_temp/vlogeg7z8q
SCMIPS/work/_temp/vlogj3g49v
SCMIPS/work/_temp/vlogjssjt9
SCMIPS/work/_temp/vlogk0tfea
SCMIPS/work/_temp/vlogkdfm3q
SCMIPS/work/_temp/vlogrhs0md
SCMIPS/work/_temp/vlogrrz5kx
SCMIPS/work/_temp/vlogs1dw87
SCMIPS/work/_temp/vlogs7gj5k
SCMIPS/work/_temp/vlogscgtns
SCMIPS/work/_temp/vlogsqi3sm
SCMIPS/work/_temp/vlogvrvh57
SCMIPS/work/_temp/vlogxsssd2
SCMIPS/work/_temp/vlogxx0436
SCMIPS/work/_temp/vlogzqi69y
SCMIPS/work/_temp/vlogzs4jm2
SCMIPS/work/_vmake
SCMIPS/控制台显示.png
SCMIPS/测试结果.png
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