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20064316212158
- 要如何区别呢？执行公用程式‘file’（例如，file /bin/bash）就对了。就ELF的程式而言，萤幕上显示出来的讯息会含有ELF的字眼；如果说是a.out的，讯息内会箝有 Linux/i386的字样。 -to how to distinguish? Implementation utility 'file' (for example, the file / bin / bash) on the right. On the ELF programs, the screen
quartusII_clock
- vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
seg71
- 这是一个很不错的CPLD数码管测试程序,从这个程序个大家得很多启发-This is a very good CPLD digital control testing procedures from the process - we have a lot of inspiration
traffic
- ＣＰＬ串口程序经过调试希望大家喜欢，很好呀大家慢慢来下载吧-CPL after serial debugging procedures hope you like, ah well we slowly download it
quartusII_traffic
- 在quartusII平台开发的一个交通灯的控制程序，并在nios平台上可以使用，所用的芯片是Stratix
vga_color
- this a sample about the VGA COLORBAR,the function of this code is show eight different colour in VGA,it s default installation is D:\\RedLogic\\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying hardware.
vga_blue_pro
- this a sample about the VGA BLUE,the function of this code is show blue in VGA,it s default installation is D:\\RedLogic\\RCII_samples, and the software environment is quatrusII 5.0,it is usefull for studying hardware.
light_controller
- 里面是一和始终的控制语言和怎么样实现的 对于用时钟控制FIR滤波器的 可以
cpld2
- TMS3205402Verilog HDL源码
Navigater_programmer.rar
- 一个机器小车的组合导航系统，GPS+惯性导航，内有DSP和FPGA的程序，比较完整,A combination of a machine car navigation system, GPS+ inertial navigation, which has DSP and FPGA program
fir
- 本设计用verilog代码实现FIR滤波器！-Verilog code of the design FIR filters to achieve!
delete
- Turbo码编码器的删除模块，此模块是CCSDS标准系的码率为1/2和1/3的删除模块-Turbo code encoder to delete module, this module is the Department of CCSDS standard rate of 1/2 and 1/3 of the delete module
fri
- 滤波器的设计的，用于FIR滤波器的设计和应用-The design of filters for the FIR filter design and application
cpld_XDS510code
- DSP仿真器源码，CPLD7000的所有工程代码，JATG边界扫描-DSP emulator source, CPLD7000 code all works, JATG boundary-scan
I2C
- vhdl一些常见的代码示例，很好的资料，含有跑马灯，蜂鸣器等代码-vhdl code for some common examples of very good information, with marquees, buzzer code, etc.
myfir
- 利用fir滤波器ip-core设计滤波器，数据为16bit，速率为61.44mhz，工作时钟为245.76mhz-The use of fir filter ip-core design of filters, the data for the 16bit, rate 61.44mhz, working clock 245.76mhz
fir
- 先用matlab得到所需滤波器的系数，将AD采样的数据经过fir滤波器后输出-First to use matlab to obtain the required filter coefficients, data from the AD sample, after the output filter through the fir
M0
- 用DSP Buider工具建一个标准工程，能了解用该工具开发的流程-With the DSP Buider tool to build a standard project, to understand the process of using the tool developed
EX22_CPLD_QQ2812_20090430
- TMS320F2812用CPLD扩展IO的程序，是我买的电路板QQ2812上的程序，经本人调试，完全可用。-TMS320F2812 with CPLD extended IO programs that I bought a program on the circuit board QQ2812, after I debug, fully available.
stream
- 实验简介： 本程序 主要在于了解用FPGA控制数据的基本方法。-Experiment Descr iption: ben cheng xu key is to understand the FPGA control data using the basic method.