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FPGA-CPLD_DesignTool(example3-4)
- FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载-FPGA-CPLD_DesignTool. 3 -4 examples procedures have requested upload download a friend in need
KCPSM3.rar
- 这个是在网上下载的picoblaze的资料，里面有些我自己写的使用方法，现在把它上传给大家。如果有需要的可以下载。个人感觉这个8位的软核开发起来有点麻烦，但是使用起来还是很好用的。对于其中的代码，归原作者所有。,This is the picoblaze downloading information, which some use to write my own methods, now upload it to you. If there is a need can be downloade
clock
- 这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clo
wavegenerator
- 产生各种波形，比如正弦波，方波，三角波等，下载的别人的，感觉不错，就上传了-Produce various waveform, for instance, square, triangle sine waves, download the others, feeling good, just upload
USB20D
- USB20D模块数据传输控制程序，包括FIFO的运用和数据上传下载-USB20D model translation
spi_master
- 用Verilog写的SPI代码，可读可写，刚仿真完，还没上板，尴尬，主要是官方限制不上传就不能下载～～～～～～～～～～～～～～ 下面的英文是百度翻译过来的，鬼畜的我都不知道啥意思～～～～(The SPI code written in Verilog is readable and writable. After the simulation is finished, it is not yet on board. Awkwardly, it is mainly that official r