搜索资源列表
taxi
- 该程序为东南大学自动化学院数字课程设计的程序，出租车计价器（08级的设计），采用VHDL实现，有详细的设计过程及最总的原理图-The program for the Institute of Automation, Southeast University Digital curriculum design process, the taxi meter (08 designs), the use of VHDL implementation, detailed design process a
POC
- 东南大学学生数字系统设计实验：用VHDL语言编写Printer与CPU互连的接口程序-Southeast University students in the experimental digital system design: VHDL language with Printer and CPU interface interconnection procedures
ourdev_185208
- 本讲义主要是讲的Verilog语言，是东南大学讲义，可以对这门语言有个初步的了解。-The lectures are mainly talking about Verilog language, the Southeast University, notes that this language has a basic understanding of.
dongnandaxuejiangyi
- 东南大学课程学习讲义 供大家参考学习 比较经典的讲义-Southeast University lecture courses for your reference to learn more classic lectures
Verilog
- 东南大学Verilog HDL经典讲义，有助于初学者的学习-Southeast University, Verilog HDL classic lectures to help beginners learn
Verilog
- 东南大学语言讲义，希望对你有帮助 很好的资料-Southeast University, language notes, I hope you have good information to help
dds--FPGA
- 基于fpga的dds实现，对应东南大学的ESD试验箱-fpga dds
verilogHDL
- verilog HDL 的课件，东南大学的课件，具有学习价值-verilog HDL courseware, Southeast University, courseware, a learning value
trafficlightsa
- 东南大学 短学期数字系统设计中的 交通灯设计 通过状态机实现-Southeast University in the short-term digital system design through the traffic light state machine design
Verilog
- 东南大学 Verilog讲义 适合初学者使用-Southeast University, Verilog notes for beginners
Test_POC
- 东南大学VHDL课程POC设计 Verilog语言-Southeast University VHDL course POC designed the by Verilog language
CPU
- 东南大学COA下实验设计CPU完整程序，可以在RAM中写程序并可观察各个输出的波形，用于检验。-south-east university COA II the design cpu lesson which you can write your own program in the cpu and also can chack the wave
traffic
- 东南大学信息学院大三编程课，VHDL相关交通灯大作业相关代码。欢迎指教改正-Southeast University, School of Information junior programming class job code for the VHDL traffic lights. Welcome advice corrections
verilog-uart-rs232
- verilog HDL 描写的uart程序 由PC端接收然后+1返回 等等 东南大学09级4系综合课程设计-verilog HDL descr iption uart program Received by the PC side and then+1 back。 SEU..
CPU
- 东南大学VHDL课程CPU设计 Verilog语言-Southeast University, CPU design Verilog language VHDL course