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add_sub_lab2
- 实验课的作业,包括半加器、全加器、加/减法器,使用逻辑图和VHDl描述,包括分析和报告。-experiment include the operation of a half adder, full adder, plus / subtraction device, and the use of logic diagram VHDl descr iption, including analysis and reporting.
jianpanshuru
- 基于vhdl的键盘输入,学校的作业,已经过验证,可用-based on the keyboard input, the school operations, which have been verified available
MyClockTest
- 这是我电子线路测试的作业,在FPGA板上实现数字钟,(Max2环境)采用VHDL语言编写,非常适合初学者。具备24小时计时,校时,低高音整点报时,定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time,
SSMS
- 汇编实习作业汇编语言实现的学生信息管理系统
elevator1
- 组成原理实验作业用VHDL实现的六层电梯程序
keyBoard
- 组成原理实验作业,用VHDL实现的简单键盘程序
Verilog_sourcecode
- 清华大学verilog hdl源码例子,作业,内含源代码,详细的文档说明,非常有用
VHDL作业-张晓峰036099149
- VHDL的四选一选择器-VHDL four elected a selector
VHDL大作业-虞益挺036100486
- 全加器的VHDL程序实现及仿真-full adder VHDL simulation program and
朱明辉vhdl大作业
- 一个双向总线的vhdl实现-a two-way bus VHDL achieve
杨帆的VHDL作业
- 带load、clr等功能的寄存器-belt load, the function clr Register
VHDL硬件描述语言作业
- VHDL硬件描述语言作业-VHDL hardware descr iption language operations
用VHDL编写的带报错和暂停控制功能的 交通灯
- 现代数字系统作业 在maxplus 10.0中调试通过
VHDL 编程
- 包含源代码
MIPS
- 组成原理大作业--基于MIPS的运算器设计,内附详细设计文档,包含设计文档和使用手册,主程序,测试程序,还有设计的框图等。实现了可以执行基本的MIPS有关运算器相关的指令共17条,用Verilog编写。-Composition Principle big operation- based on the MIPS computing design, containing a detailed design document, including design documentation and u
project2_verilog
- 简化LAPS协议实现,verilog的大作业。-Simplify the LAPS protocol, verilog great job.
lapsa
- 这是清华大学电子系的一个课程作业,要求学生用VHDL实现LAPSA协议。-This is the Department of Electronics, Tsinghua University, one course of operation, require students to achieve LAPSA agreement with VHDL.
verilog
- 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
MIPS
- MIPS处理器的组员大作业,可以直接运行,提交,环境是quartus-MIPS processor crew great job, you can run directly, the author, the environment is quartusII
4bit_buma_adder
- Verilog作业 :自己写的源码输入,补码输出的,由状态机控制的四位加法器,为保证时序,加法器模块为超前近位加法器,包含测试台,通过 Modelsim 、Synplify仿真。-Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing