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8倍频vhdl
- 该文件可用vhdl语言实现时钟8倍频，运行环境可在maxplus2和ise的仿真软件上-the document available VHDL Language 8 clock frequency, the operating environment and ideally maxplus2 simulation software
EP2C20_TEST.rar
- 内含无刷电机驱动VHDL模块，读码盘4倍频模块，并用NIOS核实现简单无刷电机闭环控制。,Brushless motor driver includes VHDL modules, reading frequency module plate 4, and nuclear NIOS simple closed-loop control of brushless motor.
beipin
- FPGA工程文件，可以实现倍频以及小数倍频功能-FPGA PROJECTION
twice_freqencey
- 用Verilog直接完成倍频的算法,经过了quartus8.0的时序仿真-Verilog multiplier used directly to complete the algorithm, as a result of timing simulation quartus8.0
beipin_top
- 次代码利用verilog HDL来描述的，可以实现2倍频功能，只是频率有一点误差。-Times verilog HDL code to describe the use of, 2 octave function can be achieved, but the frequency of a bit error.
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
twice_clk
- 对输入时钟进行2倍频 已在modelsim中通过仿真 建议进行后仿 应用上来看 是可以使用的-the function of the module is frequency multiplication，and the module had been test and verified by modelsim,so the products can be employed with 100 ease by each consumer.think you!!!!
3fp
- 奇数分频和倍频(只需修改参数就可以实现较难得基数分频和倍频)-Odd frequency and frequency-doubling (just modify the parameters can be achieved relatively rare sub-base frequency and octave)
beipin_test
- 实现任意倍数的倍频,帮助大家解决VHDL倍频问题,-The realization of arbitrary multiples of the octave, octave VHDL help people solve problems,
frequence_div
- 三分频程序,对输入的时钟信号进行分频，在此基础上可以进行倍频和分频的转化。-frequence divice
statemachine
- 基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
encoder
- 编码器信号处理 经过倍频器进行四倍频 后 同时完成鉴相 计数-the encoder single program
pll
- 是quartus2的仿真倍频电路，用于产生倍频时钟！-Is a multiplier circuit simulation quartus
Freq_4
- 伺服电机编码器四倍频源程序，已经在工程中应用。非常有用。-it is important,it has been use in my project.i hope it is useful to everyone
52250440605_AB
- 基于CPLD 的光电脉冲码盘 信号四倍频电路设计-CPLD-based electro-optical pulse encoder signals four multiplier circuit design
BPQ
- 倍频器-WE
pll
- 利用qaurtus的内的ip核定制锁相环实现对信号的倍频-The use of the ip qaurtus approved system PLL multiplier on signal
1000hz
- 产生相应的标准的上升沿触发信号，并且有2倍频功能-The rising edge of the corresponding standard generated trigger signal, and features a 2 octave
chengxu
- 4位乘法器，4位除法器，K倍频的VHDL实现-Four multipliers, four dividers, K multiplier of VHDL
jingxiang_beipin
- 实现编码器鉴向和4倍频，可用于电机测速等。(To achieve encoder and 4 times the frequency, can be used for motor speed and so on.)