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CyclonePLL
- Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。 PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟
SIG_1KHz
- 任意移相方波信号产生的VHDL代码。输入任意一个的相位偏移值就都能产生与参考方波有指定相位差的同频信号。-Square-wave signal of arbitrary phase shift generated by VHDL code. Enter any one of the phase offset can be generated on a designated phase with the reference square wave signal the same frequency
gateclockexcursionanalysis
- 门控时钟与时钟偏移分析，详解门控时钟偏移的产生和解决办法。-Gated clock and clock skew analysis Xiangjie gated clock skew of the generation and solution.
VHDLguoliangjiance
- 过零检测，输出部分有整数部分和偏移部分组成-Zero-crossing detection, the output part of the integer part and offset a part
shiyan
- OFDM中的信道均衡技术对于研究如何消除噪声干扰以及去除相位偏移的有着重要的作用-OFDM channel equalization techniques in the study of how to eliminate noise and to remove the phase offset has an important role in
phaseshift
- 移相器，任意角度偏移，包含test，经过测试-Phase shifters, any angle offset, contains test after test
divide-freq
- 基于XILINX芯片的verilog程序。调用DCM模块，完成50MHz转换75MHz，相位偏移90°-XILINX chip based on Verilog program. Call the DCM module to complete the 50MHz conversion, 75MHz, phase shift of 90 degrees
LTC2440_1
- 一款具有 5ppm INL 和 5μV 偏移的高速 24 位无延迟增量累加 (No Latency ΔΣTM) ADC LTC2440的源代码-A 5ppm INL and 5 V high speed 24 bit offset without delay increment accumulation (No Latency TM ADC LTC2440 delta sigma) source code
lcd
- lcd屏幕的驱动开发，带偏移，带屏蔽功能显示。(LCD screen driver development, with offset, with screen function display.)