Verilog写的内存控制器代码. 很好,很容易看懂-Verilog code to write the memory controller

DDR3的控制器（并带有Testbench），可烧录到FPGA中对内存进行读写，相关技术人员可在该代码上修改用于其他场合-DDR3 controller (with an Testbench), the FPGA can be burned to the memory read and write, the relevant technical staff can modify the code to be used on other occasions

改自特权同学verilog语言写sdram测试程序；支持256M内存-verilog sdram

基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.