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digital_clock
- 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习
leapyear
- 本程序用HDL语言实现闰年的判断,在ISE8.21中调试通过,比较适合初学者.
BAK
- 实现可判断闰年的万年历，未使用除法运算，可用于多种综合工具-This module work as a calendar which can judge leapyears without divider
time
- fpga万年历 vhdl语言 能实现现实时分秒年月日 及闰年判断 整点报时-every second when the fpga calendar VHDL language can achieve real date and leap year to judge the whole point of time
leap1
- 基于quartusII软件的闰年判断器的实现，运用vhdl语言描述-Software leap judgment based quartusII the realization, using vhdl language descr iption
jishi
- 用verilog语言设计了一个万年历，包括闰年判断，仿真正确(A calendar is designed with Verilog language, including leap year judgment, simulation is correct)