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占空比1：1的通用分频模块
- 用vhdl实现占空比1：1的通用分频模块，非常实用，欢迎大家下载-use VHDL to achieve the common 1:1-frequency module, a very practical and you are welcome to download
pinlvji
- 本频率计具有测周、测频、测量占空比等基本功能，能自动换档，误差为1%-the frequency meter is measuring weeks, frequency measurement, measuring the ratio of the basic functions can automatically shift error of 1%
wave_genarator_vhdl
- vhdl波形发生程序.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 各种波形的线形叠加输出。 -vhdl waveform occurred procedures. 4 achieve common sinusoidal waveform, 1.30, sawtooth, square-wave (A, B) the frequency and amplitude control
mod6_divide
- 用VerilogHDL编写的，一个占空比为50％的6分频电路-prepared using Verilog HDL, a 50% duty cycle for the six sub-frequency circuit
pwm_higt
- modelsim设计的可调占空比的方波程式-modelsim designed adjustable duty cycle of the square wave program
sanfenpin
- 这是我自己编写的三分频，也就是奇数分频，占空比为1：1，当然如果需要其它奇数分频，只要将程序里面的N和counter修改即可-This was my third prepared by the frequency, which is odd hours, frequency and duty ratio of 1:1. Of course, if the needs of other odd hours, frequency, as long as the proceedings inside
verilogshejiMiLeJIEMAQI
- 用verilog设计密勒解码器 一、题目： 设计一个密勒解码器电路 二、输入信号： 1． DIN：输入数据 2． CLK：频率为2MHz的方波，占空比为50％ 3． RESET：复位信号，低有效 三、输入信号说明： 输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成； A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。 B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保
verilogclock
- 如果不考虑占空比，直接利用计数器来进行分频，则占空比会发生变化。下面程序实现1：1的三分频。-if not duty cycle directly counter to the use of sub-frequency, duty cycle will change. Below a program : a third of the frequency.
div3
- VHDL实现50％占空比。并且是奇数分频。
three_division_VHDL_programe
- 根据上面思想写的三分频程序,1/3和50％占空比的程序.
占空比1：1的通用分频模块
- 占空比1：1的通用分频模块-1:1 generic-frequency module
1
- 多功能波形发生器 方波（占空比可调） 三角波 -Multi-function waveform generator square wave (variable duty cycle) triangular wave
fen1to7
- 这是我在ISP编程实验中独立编写的一个采用行为描述方式实现的分频器，通过两个并行进程对输入信号CLK进行8分频，占空比为1:7-This is my ISP programming experiment in the preparation of an independent descr iption of the use of behavior to achieve the prescaler, through two parallel processes on the input signa
cepin
- 本频率计具有测周、测频、测量占空比等基本功能，能自动换档-The frequency meter has a measurement weeks, measuring frequency, measuring the basic functions of duty cycle, etc., can automatic transmission
ktf
- 这是一个用VHDL编写的占空比可调的程序，对一个刚刚入门的FPGA的学员来说可以起到一个引导作用，简单但能学到很多东西-This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot
fequency
- 基于CPLD的等精度数度频率计，可以通过外设功能按键实现，频率、相位、占空比等参数的测量。-CPLD based on the number of degrees of accuracy, such as frequency meter, key peripheral functions can be achieved, frequency, phase, duty cycle measurement of parameters such as
FRE
- 用1602显示的等精度频率计，有多种功能的；可能测试占空比和周期的-vhdl
测pwm波占空比
- 基于Verilog的接受pwm波并且测量pwm波占空比(Measuring the duty cycle of PWM wave)
diver
- 根据芯片的始终频率进行分频，可调节占空比。容易实现。(The frequency division is carried out according to the chip frequency at all times, and the duty cycle is adjusted. Easy to implement.)
Verilog HDL
- 2015年全国电子设计大赛F题，时间间隔测量模块，占空比测量模块，ISE编写的verilog程序。(2015 national electronic design competition F title, time interval measurement module, verilog program written by ISE.)