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CPU
- 一个多周期CPU的完整设计,quartus平台,Verilog实现,内含实验报告,和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
20100629001
- 基于NetFPGA,实现路由转发的工程。在此工程中,可以修改路由表,实现多功能的路由功能。-Based NetFPGA, forwarding the project to achieve routing. In this project, can modify the routing table, routing capabilities to achieve multi-functional.
SG_FPGA
- 2006年电子设计竞赛二等奖,多功能函数、信号发生器核心器件FPGA内部的原理图,主要模块用VHDL代码描述,包括PLL、相位累加器、波形算法和正弦波查找表,可实现0.005Hz~20MHz的多波形信号产生,频率步进值0.005,输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic