verilog hdl蜂鸣器演奏天空之城-the Verilog HDL buzzer playing Castle in the Sky

通过FPGA开发板上的蜂鸣器实现对乐曲天空之城的演奏，编码比较简单，主要是提供一种思路-Through the FPGA development board buzzer realize music playing Laputa, coding is relatively simple, the main idea is to provide a

用verilog写的《天空之城》的乐曲，内容详细清楚，适合初学者入门-Written by verilog " Laputa" music, detailed clear for beginners

乐曲硬件演奏电路的主系统由4个模块组成： FDIV、CODE_DATA、F_CODE和DRIVER。其中，模块U1（FDIV）是分频功能将输入的6MHz的时钟信号分频成1MHZ和4Hz的信号。U2（CODE_DATA）类似于弹琴的人的手指；模块U3（F_CODE）类似于琴键；模块U4（DRIVER）类似于琴弦或音调发声器。(The main system of musical performance circuit consists of 4 modules: FDIV, CODE_DATA,