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VHDL_processor
- 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL descr iption of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
RISC_Core
- 这是用VerilogHDL描述的一个8位精简指令集处理器，包含完整代码，各种文档，以及测试环境。
CPU
- verilog编写CPU： 1. 哈佛存储器结构，大端格式； 2. 类MIPS精简指令集，支持子程序调用和软中断； 3. 实现了乘除法； 4. 五级流水线，工作频率可达80MHz（每个时钟周期一条指令，不计流水线冲突）。 -MIPS like CPU using verilog
armGPRS
- Neo_M590 AT指令集_V2.4 GPS-Neo_M590 AT command set _V2.4 information
RISC-CPU
- 用FPGA实现一个简易的CPU，采用精简指令集结构，每一条指令有16bit，高三位为指令操作数，后13位为地址，该CPU能实现8种指令操作，分别有HLT（空一个中期）ADD（相加操作）SKZ（为零跳过）AND（相与操作）XOR（异或操作）LDA（读数据）STO（写数据）JMP（无条件跳转指令）。cpu包括8个部件，分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器，各个部件之间的相互操作关系由状态控制器来控制，程序指令存放在初始rom中，本例程存放
urisc
- 实现了精简指令集微处理器的数据路径和微代码控制单元两部分的功能-RISC microprocessor implemented data path and micro-code control unit features two
risc
- RISC（reduced instruction setcomputer，精简指令集计算机）是一种执行较少类型计算机指令的微处理器。改源码是vhdl语言，能在FPGA上跑。-RISC [reduced instruction setcomputer, Reduced Instruction Set Computer] is an implementation of fewer types of computer instructions to the microprocessor. VHDL s
RISC
- RISC(精简指令集计算机)存储程序状态机的源代码-RISC (reduced instruction set computer) stored procedures source code of the state machine
multi_cpu
- 多周期CPU，mips指令集，实现了部分指令，包含测试程序，verilog-Multi-cycle CPU
cpu
- 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its perf
ARMinstructions.pdf.tar
- ARM汇编指令集详解,包括ARM7架构和大部分汇编指令，宛城布衣整理-ARM instruction set Detailed assembly, finishing Wancheng commoner
MPIS_singlecircle-12-12-completed
- MPIS单周期指令集，用VHDL编程，能够执行16条指令-MPIS single-cycle instruction set, VHDL programming instructions to perform 16
Alpha
- 一款Alpha指令集的超标量处理器的Verilog源码，是学习乱序处理器的难得资料。-A superscalar Alpha processor instruction set of the Verilog source code for a processor to learn valuable information out of order.
risc_cup
- 精简指令集CPU的VERILOG语言实现，很有用-RISC CPU the VERILOG language, very useful
CPU-Project
- CPU设计，包含基本的指令集，能执行简单的程序。考虑了CPU，寄存器，存储器和指令集之间的关系。即读写寄存器，读写存储器和执行指令。-CPU design, including basic instruction set, to execute a simple program. Consider the CPU, registers, memory, and the relationship between instruction sets. That read and write regis
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU，加上外围模块，类似与51单片机，当然还缺少很多功能，只是雏形，供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
MIPS32
- MIPS32指令集兼容的CPU模拟器设计 健词：MIPs处理器；模拟器；高速缓存；分支预-of CPU Simulator Compatible with MIPS32 Instruction Set A design scheme of a CPu simulator which is compatjble with MIPS32 instruction set is presented．
A-RISC-Design
- RISC设计：MIPS指令集控制器核，详细介绍一款32位risc-cpu。-A RISC Design:Synthesis of the MIPS Processor Core
risc
- RISC_CPU 是一个复杂的数字逻辑电路,采用精简指令集,寻址空间位 8K,它的基本部件可分成八个 基本部件 -RISC_CPU is a complex digital logic circuits, using reduced instruction set, addressing space bit 8K, and its basic components can be divided into eight basic components
cpuzl
- 实现18位操作指令实现PC指针的变化，及得到对应地址的操作指令(Implement 18 bit operation instructions to realize change of pointer and obtain operation instructions corresponding to corresponding address)