搜索资源列表
8051参考设计_Oregano System 提供_vhdl
- 8051参考设计，与其他8051的免费IP相比，文档相对较全，Oregano System 提供-8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
micro uart
- 硬件uart源程序verilog HDL，即相关文档-hardware UART Verilog HDL source, that the relevant documents
USB IPcore（带说明）
- USB IPcoreIP核，包含文档（带说明）-USB IPcoreIP nuclear contains documents (with the note)
usb_funct
- usb1.0的核，有详细的usb核的设计源码，用verilog语言编写，同时附有相关的设计文档，质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
dianti
- Verilog在maxpuls2下开发的电梯控制器的文档（包括代码），其中说明十分详尽-Verilog maxpuls2 under development in the elevator controller files (including code), It showed very detailed
color_space_converter
- verlog 编程 色彩空间转换 有测试文档-verlog programming color space conversion is testing documents
ad_DCT
- verilog 编程 有测试文档 基于查表结构实现 离散余弦变换dct 来源：opencores -Verilog Programming is based on the test documents Lookup structure for a discrete cosine transform Extra Source : opencores
entropy_coding
- 用verilog 描述的嫡编码(entropy coding) 应用于图像压缩编码 有测试文档 -using Verilog His descr iption of coding (entropy coding) for image compression test files are encoded
verilog_jpeg
- 用verilog 描写 应用于数字图像压缩系统--jpeg 有测试文档-using Verilog descr iption applied to digital image compression system -- a test jpeg files
FSKmodemodulateVHDLprogramme
- FSK调制与解调的vhdl源代码与仿真指导，是word文档打开。-FSK modulation and demodulation of VHDL source code and simulation of the guide is the word document open.
CRC32_VHDL_SOURCE_CODE
- 这是利用VHDL编写的一个CRC32的代码，文档只有代码，具体原理请参考其他文献-This is the use of VHDL prepared a CRC32-code, the document is only a code Please refer to specific tenets of other literature
USB2.0IP_core_Verilog
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
CRC_VHDL
- 可配置CRC参考设计 xilinx的ip，参考设计文档CRC_xapp562[1].pdf，VHDL语言编写的代码，包含仿真所需文件-configurable CRC Reference Design xilinx the ip, CRC_xapp562 reference design document [1]. pdf, prepared by the VHDL code The simulation includes the necessary documents
usb11_systemc
- USB 1.1 PHY的代码，systemc语言 USB 1.1 PHY的代码，systemc语言,包括基于systemc语言的testbench ，和相关的doc文档-USB 1.1 PHY code systemc language USB 1.1 PHY code, systemc languages, including systemc based testbench language, doc and related documents
clock_top2
- 数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
FPGAFSK该文档是基于FPGA的2FSK调制程序
- 该文档是基于FPGA的2FSK调制程序，包含仿真结果-The document is based on FPGA-2FSK modulation process, including simulation results
MusicPlayer
- 用vhdl语言实现，从sdisk上读取并播放音乐的功能。 附有详细的设计文档说明-Using VHDL language, from sdisk read and play the music functions. Accompanied by a detailed descr iption of the design documents
compare8
- 一个用Verilog语言实现的八位二进制数比较器。包含工程文件和实现文档。-One with the Verilog language implementation of the eight binary comparator. And the achievement of the document contains the project file.
Altera官方FPGA电机控制的中文文档
- Altera官方FPGA电机控制的中文文档，很不错的参考资料(Altera Official FPGA Motor Control Chinese Document, Good Reference)
DC Synopsys Workshop
- Design Compiler 工作台教程文档 操作手册(Design Compiler Workshop Tutorial Document Operation Manual)