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Output_Decoded_FSMs
- 有限状态机的并行编码,采用并行编码可以有效提高系统最高频率,次态时间充分被利用.
FPGA控制AD程序,ADC,DAC转换接口
- FPGA控制AD程序,ADC,DAC转换接口.rar 有限状态机控制AD采样.rar,FPGA control AD procedure
FSMLibrary
- 有限状态机源码，最近在做一个项目需要用到状态机，自己研究了一下，将原来的状态机封装了，做了一些修改，实现了一个比较好用的状态机。里面包括测试工程，用例-Finite state machine source code, most recently doing a project needs to use state machines, their study a little, the original state machine package, and made some modificat
control_fsm_rtl.vhd
- ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机 ALU 有限状态机-ALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSMALU FSM
statemachine
- 用VHDL实现的有限状态机，还有modelsim仿真文件，及仿真结果-VHDL implementation using finite state machine, there modelsim simulation file, and the simulation results
fsm
- VHDL新手入门：有限状态机练习（三段式结构）-VHDL Getting Started: Finite state machine exercises (three-stage structure)
fsm
- 有限状态机工作原理、设计方法、步骤等精要说明-Finite state machine working principle, design method, such as Essentials of steps to explain
VHDL
- 各种有限状态机的设计。 VHDL源代码。 -All kinds of finite state machine design. VHDL source code.
UART
- UART是一种广泛应用于短距离、低速、低成本通信的串行传输接口.由于常用UART芯片比较复杂且移植性差,提出一种采用可编程器件FPGA实现UART的方法, 实现了对UART的模块化设计.首先简要介绍UART的基本特点,然后依据其系统组成设计顶层模块,再采用有限状态机设计接收器模块和发送器模块,所有功能的实现全部采用VHDL进行描述,并用Modelsim软件对所有模块仿真实现.最后将UART的核心功能集成到FPGA上,使整体设计紧凑,小巧,实现的UART功能稳定、可靠. -UART is a wi
state
- verilog HDL下有限状态机（FSM），麻雀虽小，但五脏俱全！值得一看-under the verilog HDL Finite State Machine (FSM), the sparrow may be small, but is a fully-equipped! Worth a visit! !
youxianzhuangtaiji
- 有限状态机的说明以及源代码 有限状态机的说明以及源代码-FSM
state_mm
- 有限状态机源码，verilog语言编写。非常详细的示范了FSM状态机的编写。-Finite state machine source code, verilog language. A very detailed model of the FSM state machine preparation.
ktkzxt
- 利用有限状态机描述的空调控制系统，温度状态有过高、过低、正好三种状态，控制方式有升温和制冷两种；设计了温度传感装置-The use of finite state machine described in the air-conditioning control systems, temperature conditions are too high, too low, just three states, the control methods are two kinds of heating
FSM
- 有限状态机设计指导,详细介绍了设计状态机过程中的有关经验，以及各种状态机设计的相互优劣对比-Finite state machine design guidance, details of the design state machine during the relevant experience, as well as various advantages and disadvantages of each state machine design comparison
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
USE_FSM_DEDIGN_SRAM
- 用FSM（有限状态机）设计SRAM的VHDL语言-With the FSM (finite state machine) design of the VHDL language SRAM
Verilog-HDL
- 这是关于VERILOG HDL的有限状态机的源码，大家参考参考，应该有好处的。-This is about VERILOG HDL source code for finite state machines, we refer to the reference, it should be good.
design
- 使用有限状态机完成序列检测，是FPGA开发中的基础程序(sequence detection with state mation)
状态机
- 本代码跟据状态转移图，通过verilog实现了一个有限状态机。(This code implements a finite state machine with the state transition graph through verilog.)
FiniteStateMachine
- 使用VHDL实现的有限状态机的ISE工程 ise版本14.7(Finite State Machine based on VHDL)