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边沿检测
- 边沿检测电路程序 verilog
edge
- 图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换-Image processing edge detection of VHDL source code, the algorithms used are garbor transform
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
xiaodou2
- 基于脉冲边缘检测的按键消抖模块verilog-Key consumer shake module verilog
EDA3add
- 序列信号发生器与检测器设计：用状态机设计实现串行序列检测器的设计，先设计（可用原理图输入法）序列信号发生器产生序列：0111010011011010；再设计检测器，若检测到串行序列11010则输出为“1”，否则输出为“0”，并对其进行仿真和硬件测试。-Sequence signal generator and detector design: The Design and Implementation of a serial sequence of state machine design of
serial_check
- 本实验需要实现一个序列检测器，用来检测输入的串行位流是否和程序设定的位串相一致，若一致则在验证波形的出现一个高电位来表示。本实验需要验证的位串是“101011”。-In this study, need to implement a sequence detector, to detect whether the input serial bit stream and procedures consistent set of bit strings, if the same occurs in
edge_detector
- 基于CPLD的数字图像边缘检测算法的实现(VHDL源程序)-EDGE DETECIOR
CANNY
- 对特定图片进行canny边缘检测。首先是高斯模糊，然后sobel算子处理，再局部极大值确定，最后阈值判断。(Canny edge detection for a particular picture. The first is the Gauss fuzzy, and then the Sobel operator is processed, and then the local maximum is determined, and finally the threshold is judged
2_key
- 利用两个相差一个时钟周期的寄存器进行&~运算，进行下降沿的检测。可用于按键消抖等。(Two regs are used to detect xiajaingyan with &~, and it can be used to switch debounce)
project_2_10010
- 检测的序列10010的一个小程序，用vivado做的(A program for detecting sequence '10010' powered by vivado 2014.4)
SOBEL
- 基于VHDL图像边缘检测，可在在仿真波形上看出其边界值(Based on VHDL image edge detection, the boundary value can be seen on the simulation waveform)
超声检测数据叠加算法
- 将超声检测所得波形取正端波形，移位叠加两组数据，观察叠加后缺陷的变化
Edege_detect
- 边沿检测模块，实际项目中验证； 功能：上升沿、下降沿检测(Edege detect module Func : rising_edge falling_edge detect)
Verilog的边沿检测技术_设计源代码
- 波形数据上升下降沿的检测程序，已经经过仿真验证(The detection program of the rising descending edge of the waveform data has been verified by simulation)
device_dri
- 该程序结合iic驱动程序，可用自动检测硬件的寄存器配置参数是否正确，项目中已使用过(With the IIC driver, the program can automatically detect whether the hardware's register configuration parameters are correct. The program has been used in the project.)
Audio_whistle_suppressor
- 探讨了一种数字移频法啸叫检测与抑制音频功率放大实验测试系统设计方案，用来实现带啸叫检测与抑制音频功率放大．系统以 FPGA 为控制核心(This paper has designed a testing system for an audio power amplifier with howling detection and suppression which is used to achieve howling detection and suppression audio power am
sobel
- 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Ve
HK-2+blood type
- 输入血型，进行匹配与判断，检测是否与受血人的血型匹配，无安全隐患，可以进行输血(Blood type input, matching and judgment, detection and blood type of the recipient of blood matching, no safety risks, blood transfusion can be carried out)
运动目标检测
- 通过fpga开发板控制ov7670摄像头检测目标 实现运动检测(shi xian yun dong jian ce .)