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VHDL.rar
- 正弦信号发生器具有频率调节功能。采用VHDL编程实现。,Sinusoidal signal generator with a frequency adjustment function. Using VHDL programming.
ddfs.rar
- 基本FPGA的DDS信号发生器，可产生1-1MHZ任意频率的三角波，方波，锯齿波，正弦波,Basic FPGA-DDS signal generator, can produce 1-1MHZ arbitrary frequency triangle wave, square wave, sawtooth, sine wave
sine-generator
- 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
FINALWORK
- 简易信号发生器 可产生正弦波、方波、三角波、锯齿波 周期可调 verilog-Simple signal generator can produce sine, square, triangle wave, sawtooth-cycle adjustable verilog
sine
- Verlog语言描述的正弦信号发生器的源代码可以方便的实现长生正弦信号-Language Verlog sinusoidal signal generator described in the source code can easily achieve the longevity of the sinusoidal signal
sin125
- 用FPGA实现DDS的信号发生器（正弦波125kHz）-Using FPGA to achieve DDS signal generator (sine wave 125kHz)
FPGA_signal_general
- 摘 要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。 关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are giv
jiyuVHDLyuyandehanshuxinghaofashengqi
- 好用的函数信号发生器，能产生多种波形，例如，正弦波，方波，锯齿波，阶梯波。-Useful function signal generator, can produce a variety of waveforms, for example, sine wave, square wave, sawtooth, wave ladder.
signal_generator
- 基于vhdl的多功能函数信号发生器的设计，能实现三角波、方波、正弦波。-VHDL-based multi-function signal generator design, can achieve the triangular wave, square wave, sine wave.
FPGA_DDS
- 本文介绍了如何用VHDL进行DDS的设计，其中关键的相位累加器，正弦信号发生器等用VHDL描述-the DDS is depend on the fpga ,and we descr iption it use the vhdl
wave_generator
- 基于cycloneII的信号发生器，产生正弦波、方波、三角波，人机界面十分友好，可方便地进行波形切换-CycloneII based on the signal generator to produce sine wave, square wave, triangle wave, a very friendly man-machine interface can be easily switched waveform
data_rom
- 正弦信号发生器，用VHDL来完成，抗干扰能力较强，-Sinusoidal signal generator, using VHDL to accomplish, a strong anti-interference ability,
FPGA_VHDL_sinusoidal_function
- 该文件包含基于VHDL的正弦信号发生器的设计源码-This file contains the VHDL-based design of sinusoidal signal generator source code
example10
- 利用直接数值合成 DDS 原理驱动 dac0832 实现正弦波输出。 输出可以通过示波器观察。-The use of direct numerical synthesis of theory-driven dac0832 achieve DDS sine wave output. Output can be observed through the oscilloscope.
Sinusoidalsignalgenerator
- 用硬件描述语言vhdl中的ROM模块实现正弦信号发生器 -Sinusoidal signal generator
sin
- QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
sine-generator
- ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
SG_FPGA
- 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the devic
dds信号发生器
- dds正弦信号发生器源代码，适合处于学VHDL学生查阅
Signal-Generator-VHDL-design
- 信号发生器VHDL设计 波形可选：正弦(sine)，方波(sqr)，锯齿波(jc_de和jc_in两种)，三角波(sanj)和阶梯波(stair)信号模块-Optional waveform signal generator VHDL design: sinusoidal (sine), square wave (sqr), sawtooth (jc_de and jc_in two kinds), triangle wave (sanj) and staircase (stair) sig