搜索资源列表
SDRAMcontroller
- 西安电子科大的一片论文，主要讲述了SDRAM控制器的设计思路和方法-a paper about the information and descr iption of SDRAM controller
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
DA-FIR-FPGA
- 详细介绍了分布式算法FIR的设计，对于用FPGA实现FIR的设计具有指导意义。来自华中科大。-Detailed design of a distributed algorithm FIR, FPGA implementation for the FIR design with a guide. From HUST.
VHDL-and-DLC-design
- VHDL硬件描述语言与数字逻辑电路设计 西安电子科大出版-VHDL hardware descr iption language and digital logic circuit design Xi' an Electronic Science and Technology Publishing
UESTC_VHDL_PPT
- 电子科大通信抗干扰实验室何旭老师的VHDL课程-Electronic Science and Technology Laboratory He Xu teacher communication interference VHDL course
VHDL_pinlvbiao
- VHDL实现数字频率表功能，针对中科大复杂数字系统设计大实验进行功能补充-VHDL digital frequency table for the USTC complex digital systems design experimental functional supplement
VLSI-Project-Median-filer
- FPGA和ASIC实现的图像中值滤波模块，各模块的仿真结果以及MATLAB,Modelsim联合仿真。这是中科大超大规模集成电路设计优化的final project。附有最终版的report和presention。-FPGA and ASIC implementation of image filtering modules, each module of the simulation results and MATLAB, Modelsim co-simulation. This is the
Digital-system-EDA-test-paper
- 电子科大数字系统EDA技术期末考试题,13-14年-Digital system EDA test paper of UESTC