搜索资源列表
jtag
- verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
boundaryscan1949.7
- 边界扫描程序调试案例，用于电路板自动测试中-Case of boundary-scan debugging, automated test for circuit boards
Fign
- FPGA嵌入式边界扫描总线控制系统设计FPGA embedded boundary-scan bus control system design-FPGA embedded boundary-scan bus control system design
tapcontroller
- FPGA边界扫描时的TAP控制器，这个是工程文件，带有modelsim仿真-FPGA boundary scan when the TAP controller, this is a project file with modelsim simulation
jtag
- verilog语言编写的jtag（边界扫描模块），初学的时候可以-verilog language jtag (boundary scan module), a novice when you can look
Boundary-Scan-Architecture
- 边界扫描技术相关资料，官方说明，含各个模块的介绍。很有参考价值。-Boundary-Scan Architecture
JTAG
- 边界扫描技术相关资料，含各个模块的介绍。很有参考价值。-JTAG TAG CONTROLLER
1
- 基于USB接口的边界扫描测试控制器设计,很实用，值得参考。-jtag tap controller