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juzhenjianpan
- 基于FPGA，在quartus上，用WHDL语言和原理图设计的矩阵键盘显示电路。完整项目。-Based on FPGA, quartus, with WHDL language and principles of map design matrix keyboard display circuit. Complete the project.
chuzuchejifei
- 基于FPGA，在quartus上，用WHDL语言和原理图设计的出租车计费器。完整项目。-Based FPGA, quartus, with WHDL language and principles of map design taxi meter. Complete the project.
video_add_program
- 改文件为OPENHW嵌入式大赛的获奖项目，主要做的视频叠加，很有参考价值-Change the file for OPENHW embedded contest winning projects, mainly to do video overlay, great reference value
vga_focus
- 该项目为OPENHW嵌入式大赛的获奖项目，用FPGA存储和用VGA来显示，带整个工程文件。可直接下开发板中去-The project is OPENHW embedded contest winning projects, FPGA storage and VGA display, with the entire project file. Directly under development board
e2prom_rd
- Verilog HDL 读取EEPROM项目的详细构建-Verilog HDL EEPROM read the detailed construction
i2c_reg
- 用verilog实现的一个从机的I2C通信模块，测试通过可用，已经在项目用的了！-Using verilog achieve a slave I2C communication module, the test is available, has been used in the project!
myproj
- 使用vhdl语言设计波形发生器，产生正弦波，方波，三角波，锯齿波，实现频率，幅度可调。项目包附有设计说明和资料。-Waveform generator using vhdl language design, produce sine, square, triangle, ramp, realize the frequency, amplitude adjustable. Project package with design specifications and data.
reg8b
- 8位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-8 registers design using VHDL language for DDS signal source project
adder16b
- 16位寄存器设计，用VHDL语言编写，用于DDS信号源中项目-16 registers design using VHDL language for DDS signal source project
chengfaleijia
- verilog 乘法累加器 包括工程项目及仿真波形图-verilog multiplier-accumulator including the project and the simulation waveform
FPGA_Verilog-
- 关于VHDL程序设计的书籍，经典免费，书中主要描述 Verilog 语音的介绍以及项目例程-About VHDL programming classic books, free of charge, the book describes the Verilog voice introduction and project routines
fft
- FPGA实现FFT算法的源代码及工程文件，此工程为ISE工程项目。有详细的说明，可以运行。-FPGA Implementation of FFT algorithm source code and project files, this works for the ISE project. There are detailed instructions, you can run.
cordic
- verilog实现的cordic算法，很好的代码，实际项目中使用过的。-verilog cordic
Cyclone4_115_TV
- 基于Altera cyclone4_115芯片下的完整VGA端口开发工程，包括VHDL源文件，和项目工程文件，对于FPGA下的VGA端口开发很有参考价值。-Based on Altera cyclone4_115 chip under full VGA port development projects, including the VHDL source files, and project files, the VGA port for FPGA development of great r
Cyclone4_SD_Card_Audio_Player
- 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.
Cyclone4_115_IR
- FPGA下红外收发项目工程，基于cyclone4 芯片，包括项目verilog源码已经sof下载文件，对于基于fpga的红外模块开发很有参考价值。-Project under infrared transceiver FPGA based cyclone4 chips, including project sof verilog source code has been downloaded files for fpga-based infrared module development of
ECE572_SS
- 扩频通信开源项目接收机的源码，对于工程很有帮助，附带说明文档ppt-Source spread spectrum communication receiver open source projects for engineering helpful, with documentation ppt
PCI9054
- PCI总线芯片PCI9054本地总线的FPGA控制逻辑。 硬件架构为PCI9054+双口RAM+FPGA。 使用USERo清中断。 该逻辑以在项目中应用。-PCI bus FPGA chip PCI9054 local bus control logic. Hardware architecture PCI9054+ dual-port RAM+ FPGA. Use USERo clear interrupts. The logic to apply in the pro
AD9957-SPI
- 内含AD9957的SPI配置程序，输出为单音。目前该程序仅给出三个寄存器的配置，如有需要，简单阅读程序，即可对程序进行修改，本人项目中使用的为该配置程序，能成功输出各种MPSK波形。-The AD9957 contains SPI configuration program, the output is mono. Currently, the program gives only three registers configuration, if necessary, a simple rea
matongbu
- 调制信号解调时，从解调出的信号中提取码元同步时钟，以获得最佳的抽样判决时刻。本程序采用超前-滞后同步法，计数器时钟为16倍的码元时钟。 该程序同步效果很好，已使用在项目中。-Demodulating the modulated signal, extracts the symbol clock from the synchronizing signal demodulated in order to obtain the best sampling time judgment. This p