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VHDLTest_us
- 你会做这些题吗？这是来自国外的测试题-you do that? This is a test from abroad that!
EP1C3_12_9_DDS
- 直接数字式频率合成器(DDS)设计实验(电子设计竞赛赛题) 其它详细资料说明请参考 http://www.kx-soc.com-direct digital frequency synthesis (DDS) experimental design (Electronic Design Contest tournament title) said other details Please refer to prescribed http://www.kx-soc.com
DM9000A_IPcose
- 如题：dm9000aＩＰ核，经过验证，可用
2011年电子设计大赛e题《简易数字信号传输分析仪》
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，实现后端采样同步时钟-E Electronic Design Contest 2011 problem " simple digital signal transmission analyzer" verilog source code sample to achieve the back-end clock synchronization
b_pro3_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
8b10b
- 如题,原始8B10B编码，仿真通过。真麻烦，要说那么多废话-as title
97B
- 这是电子设计大赛的97年b题简易数字频率计的fpga一种做法。-This is Electronic Design Competition 1997 b problem simple digital frequency meter fpga practice.
addr8
- 8位加法器VHDL源程序，实验题能够在EDA开发系统中运行-8-bit adder VHDL source code, experimental questions can be developed in the EDA system to run
my_uart_top
- 实现的功能如题，就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。上位机用的是老得掉牙的串口调试助手-To achieve the functions such as title, that is, to achieve FPGA receives data from the PC, and then receive data back fat. Using a UART serial port protocol to send and recei
FPGA_Interview_Book_Title
- 在信威dsp软件面试、汉王笔试、扬智电子笔试、新太硬件面题时的题目-Xinwei dsp software in the interviews, written Hanwang, ALi electronic written, the new hardware side too, when the topic title
sodamachine
- 刚做完的一个实验，传上来分享一下 写的一般，请见谅 原题是麻省理工的一道EDA设计题：设计一个自动售货机系统，卖soda水的，只能投进三种硬币，要正确的找回钱 数。 （1）用到有限状态机；（2）用VHDL编程 -Just finished an experiment, transfer up to share writing in general, please forgive the original question is a Massachusetts Institute of T
filter1
- 题为基于CSD编码的FIR数字滤波器设计.该滤波器具有线性相位,系数减半.采用VHDL语言编写.是我们EDA课程的作业,得了优.希望对大家有用-Entitled based on CSD code FIR digital filter design. That the filters have linear phase, coefficient half. Using VHDL language. Is the EDA program operations, got excellent. Hop
taxi4
- 本程序是天华杯模拟题中出租车计价器源程序，由本人编写，经测试基本满足要求-This procedure is the day China Cup title in the taxi meter analog source, which I am prepared to meet the basic requirements have been tested
kaoshi
- eda上机考试题 分享 包括分频计 计数器 等不同类型的题-eda-on exam questions to share, including frequency counter, count the different types of questions
Verilog-HDL.RAR
- 采用Verilog HDL语言编写的数字频率计，可以作为不错的练习或课设题-vhdl langue
fft_IPcore
- 如题 基于FFT的ip核系统程序 经测试好用-Such as the nuclear issue through FFT-based test easy to use ip
digital_sigal_generator
- 全国大学生电子设计大赛源代码，Verilog HDL ，2011年最后一题，即E题代码-National Undergraduate Electronic Design Contest source code, Verilog HDL, 2011 the last one question, that question the code E
e_pro_restored
- 2011年电子设计大赛e题《简易数字信号传输分析仪》verilog源代码，分信号源和分析仪两部分-2011 electronic design competition e question the simple digital signal transfers analyzer "verilog the source code, and the points the signal source and the two parts analyzer
m_serial
- x^8+x^4+x^3+x^2+1, 这个本原表达式，m序列，国赛中的一个题，用verilog编写，里面有详细讲解，经过我认真验证。-x^8+x^4+x^3+x^2+1 m serial
2011-diansai-E
- 2011年 电赛 E题 简易数字信号传输性能分析仪FPGA信号发生部分 包括m序列，伪随机序列，曼彻斯特编码 程序 和单片机部分程序-2011 CEC E title simple digital signal transmission performance analyzer FPGA signal part of the program and single-chip part of the program