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fenpinqi.rar
- 用VHDL语言设计分频器要求是将128赫兹的脉冲信号经过分频器分别产生64赫兹，32赫兹，16赫兹，8赫兹，4赫兹, 2赫兹，1赫兹，0.5赫兹的8种频率的信号,Divider design using VHDL language requirement will be 128 Hz pulses were generated through divider 64 Hz, 32 Hz, 16 Hz, 8 Hz, 4 Hz, 2 Hz, 1 Hz, 0.5 Hz frequency of the
Walsh
- 利用ISE编写的产生WALSH码的verilog程序，简单易懂，稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
16X64dianzhen
- 16*64点阵程序，运用串行传输数据，移位寄存器接收数据，硬件电路连接简单-16* 64 lattice procedures, the use of serial transmission of data, receive data shift register, hardware circuits connected simple
sram
- 实现单端口SRAM，地址4比特即一共16个寄存单元，数据4比特说明每个单元有四个寄存器，一共64个D-Single-port SRAM, 4-bit address that is a total of 16 storage units, data 4-bit instructions each unit has four registers, a total of 64 DFF
ofdmbaseband
- the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of e
Analog-to-digital-converter
- 模数转化器，64位双精度的模拟输入值，16位数字输出-Analog to digital converter, 64-bit double-precision analog inputs, 16 digital outputs
clk_div2_4_8_16_32_64_128
- Divide by 2,4,8,16,32,64,128 clock divider
AnumberrT
- AT89S52控制64*16双基色点阵led显示数字数字通过过自摸取出数组8*16硬件环境：595，AT89S52,138 -AT89S52 control 64* 16 dual color dot matrix led display digit number by Zimo remove an array of 8* 16 Hardware Environment: 595, AT89S52 is, 138
A158883834166b
- 关于16行64列的LED点阵，能够左右移动，程序源码简简单易懂易懂，希望大家来下载 可直接使用。 已通过测试。 -About 16 rows of 64 LED dot matrix, be able to move around the program source code, the simple and easy to understand and easy to understand, want to download can be used directly. Has been t
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
ddr2_sdram_latest.tar
- 1.初始化-Sequenz的RAM 2. Automaic写Sequenz（写入16数据字每一个64位的RAM） 3.自动读Sequenz（从RAM读出的第一个数据字）-1. Init-Sequenz for the RAM 2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM) 3. Automatic Read-Sequenz (reads the first Dataword the
dianzhen1616
- 16*16点阵动态滚动显示VHDL四个字母 共有5个模块，4个子模块，top是顶层模块 1.control，产生地址信号，用来读取数据 2.data_store,64组数据，4*16，根据输入地址来输出对应的数据 3.freq，分频模块，由50M主时钟进行分频，得到系统所需的各个频率 4.display,控制点阵模块，将得到的数据进行输出-display VHDL on 16*16 dot matrix
bch_dec_enc_dcd
- 关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现-On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation