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  1. multi_cycle_cpu

    0下载:
  2. 多周期cpu,multi_cycle_cpu,南京大学计算机系计算机组成原理实验-Of multi-cycle cpu, multi_cycle_cpu, Nanjing University Department of Computer Science Computer principle experiment
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-29
    • 文件大小:11.16mb
    • 提供者:sunying
  1. alu_arm_alu_mips

    0下载:
  2. 加法器的arm实现和mips实现,alu_arm,alu_mips,南大计算机系计算机组成原理实验-Adder arm to achieve and realize mips, of alu_arm alu_mips, Nanda, Department of Computer Science Computer principle experiment
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1.12mb
    • 提供者:sunying
  1. 1MEMOCODE4_dave_contest

    0下载:
  2. Hardware Acceleration of Matrix Multiplication a Xilinx FPGA Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan Computer Science and Artificial Intelligence Lab Massachusetts Institute of Technology Cambridge
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-16
    • 文件大小:120.77kb
    • 提供者:lance
  1. vhdl-(1)

    0下载:
  2. VHDL book The VHDL Cookbook First Edition July, 1990 Peter J. Ashenden Dept. Computer Science University of Adelaide South Australia
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-08
    • 文件大小:388.51kb
    • 提供者:heiji
  1. alu

    0下载:
  2. In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors conta
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-02
    • 文件大小:2.36kb
    • 提供者:Andrew
  1. Ji-jia-qi

    0下载:
  2. 用 verilog实现的基于FPGA的出租车计价器,只有源代码,没有相关说明-The source is Taximeter which is complishment by language verilog on FGPA, some college students whose major is computer science may be related to it
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:14.37kb
    • 提供者:姚小明
  1. Multiplier-shifter-design-tradeoffs-in-a-32-bit-m

    0下载:
  2. excellent paper which is about the design of MIPS Architecture in the field of computer science and technology
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:729.44kb
    • 提供者:trial6
  1. ARM_register

    0下载:
  2. ARM寄存器的设计,南京大学计算机系计算机组成原理实验内容-ARM register designs, Nanjing University Department of Computer Science, Principles of Computer Organization experiment content
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-17
    • 文件大小:4.01mb
    • 提供者:sunying
  1. shifter_arm

    0下载:
  2. 桶形移位器,8位,16位,32位,含ARM桶形移位器。南大计算机系计算机组成原理实验-Barrel shifter, 8, 16, 32, including the ARM barrel shifter. NTU Department of Computer Science Experimental Computer System
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.83mb
    • 提供者:sunying
  1. single_cycle_cpu

    2下载:
  2. 单周期CPU,single_cycle_cpu,南京大学计算机系计算机组成原理实验-Single-cycle CPU, single_cycle_cpu, Nanjing University Computer Science Department of Computer Composition Principle Experiment
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.76mb
    • 提供者:sunying
  1. pipeline_cpu

    0下载:
  2. 流水线cpu,pipeline_cpu,南大计算机系计算机组成原理实验-Pipeline cpu, pipeline_cpu, Nanjing University Department of Computer Science Computer Composition principle experiment
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-28
    • 文件大小:10.65mb
    • 提供者:sunying
  1. frequency-meter-of-same-precision

    0下载:
  2. 本系统采用了以Altera芯片EPF10K10LC84-4和单片机仿真器伟福H51/S POD-H8X5X 为核心,同时辅有8位七段数码管和7219数码管驱动芯片。设计使用max+plus2,keil3和伟福开发环境,其中FPGA计数功能,FPGA与单片机的接口通信,单片机计算数据并驱动显示模块等功能。 系统实现了4hz~12Mhz频率的测量,并利用科学计数法显示。测量相对误差在0.005 以内,每个频段均显示6位有效数字。 本系统的特点在于高精度,显示界面科学友好。硬件部分VHD
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-27
    • 文件大小:540.46kb
    • 提供者:穆环
  1. traffic

    1下载:
  2. 红绿交通灯。哈工大计算机学院数字逻辑大作业,09籍~~~可以直接用的哈-Red and green traffic lights. Harbin Institute of Computer Science, the digital logic operations, 09 Ji ~ ~ ~ can be used directly
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2016-12-21
    • 文件大小:445kb
    • 提供者:wudan
  1. CJ2

    0下载:
  2. 关键词:清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码,为学弟学妹造福-Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-11-30
    • 文件大小:1.65mb
    • 提供者:jin
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