搜索资源列表
FIFO_counters_VHDL.rar
- FIFO和计数器以及时钟控制，用于程控交换机教学，与DSP和ADDA芯片配合完成程控交换机功能,FIFO and counters and clock control, program-controlled switchboard for teaching, with the DSP and complete ADDA chip with program-controlled switchboard function
ADDA_control_VHDL
- VHDL语言的ADDA（模数数模置换）控制，用于程控交换机功能，与DSP和ADDA芯片配合-VHDL language ADDA (analog-to-digital digital-analog replacement) control, for program-controlled switchboard function, with the DSP and ADDA chip with
ad2902
- AD2902是一款adc芯片，适用于速度要求比较高的系统，本代码开发了FPGA控制AD2902的程序。-AD2902 is a kind of ADC chip.it is a fast speed chip. so it is usually used in FPGA or DSP system.
Six-phase-Motor-Based-on-DSP
- 设计了六相感应电机的控还原 制平台的硬件结构及其各个组成部分,控制平台结构主要由DSP控制系统和主驱动电路系统以及检测电路系统组成。控制系统采用TI公司的TMS320F2812快速DSP控制芯片。 -This paper designs the hardware structure of the six-phase motor control system and introduces every component. The control platform consists
cpld1
- 通过DSP控制CPLD与网口，灯及USB接口芯片的通讯与指示-CPLD and DSP control network through the mouth, lights and USB interface chip communication and instructions
mcrmc
- 风电发电中无功补偿控制板ＣＰＬＤ程序的编写，主要配合ＤＳＰ和ＡＲＭ进行时序控制，以及PWM波的产生。-Wind power generation in the CPLD control panel reactive power compensation procedures for the preparation, mainly with the DSP and ARM timing control, and PWM wave generation.
tst_saa7113h
- 飞利浦的视频解码芯片SAA7113H的Verilog控制源代码，该源代码加入了SRAM和DSP，很值得参考-The Verilog control code of Philips video decoder chip SAA7113H , the source code combine the interface of SRAM and DSP, it is worth considering
FPGA-dsp-motor-control
- 基于FPGA的LAMOST多电机控制驱动系统-Based on the FPGA LAMOST motor control and drive system
DSP_cpld
- dsp控制cpld的代码，包括cpld内部逻辑和与外部的链接引脚-the dsp control the cpld code, including the cpld internal logic and external link pin
FPGA-SRC
- 用于DSP+FPGA开发系统，可用于采集一帧图像并控制SRAM、SDRAM数据存取。-Used in DSP+ FPGA development system, to capture an image and control the SRAM, SDRAM data access.
hpi
- 实现FPGA控制DSP的HPI接口，使用verilog接口-Achieve FPGA DSP HPI interface control, use verilog interface
HAPF_SLAVE2
- 高压链式SVG控制用FPGA的verilog程序,其中包括SPI，16路SCI同步通讯模块程序，保护自锁功能程序，基于滞环的无功功率检测和补偿策略；还包括FPGA和DSP之间通过总线方式进行数据的快速交互等；程序完整-SVG high voltage chain of verilog FPGA control procedures, including SPI, 16 road SCI synchronous communication module procedures to protect
fpga
- pid算法控制电机运动，实现fpga与dsp的双口RAM通信(PID algorithm to control motor movement, the realization of FPGA and DSP dual port RAM communication)
DSP+FPGA步进电机开发板资料
- DspMotor里是dsp步进驱动源码。环境 ccs3.3 ；.FpgaMotorControl是fpga光栅尺采集源码。环境 ISE10.1(DspMotor is the DSP stepping drive source. Environment CCS3.3;.FpgaMotorControl is the source of FPGA grating ruler. Environment ISE10.1)
基于DSP和FPGA的通用数字信号处理系统设计
- 利用DSP配合FPGA为硬件架构，以DSP为数据处理核心，通过FPGA对USB、ADC和DAC等外围设备进行控制，并可实现频谱分析、数字滤波器等数字信号处理算法。(With DSP and FPGA as the hardware architecture and DSP as the data processing core, the peripheral devices such as USB, ADC and DAC are controlled by FPGA, and the digi