利用VHDL实现8位数据加法，完成方法为实验原理图直接搭建。-VHDL 8-bit data addition, the completion method for experimental schematic structures directly.

镁光MT9基于FPGA图像采集模块，该模块可同时采集两路视频信号。其包括完整的时序和接口、ddr2内存数据写入和存储、qsys系统的搭建、FPGA与NIOS II联合设计-Micron MT9 based on FPGA image acquisition module, the module can simultaneously capture two video signals. Including the complete timing and interface, ddr2 memory