Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations

here it is a file which is consist of design of a MIPS pipeline in verilog, it also has test part an it work perfectly. the code is written in good way to understand it easily