搜索资源列表
Verilog-HDL
- 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples w
6040404
- Signal generator final report
EWB_eclock
- 用方波信号发生器发出1HZ的稳定的方波信号作为CP信号输入 ,秒计数器满60向分计数器进位,分计数器满60向小时进位,小时计数器按“23翻0”规律计数，计数器经译码器送到显示器；计数出现误差可用校时电路进行校时、校分、校秒。并具有可整点报时与定时闹钟的功能。 本数字钟的功能列表如下： 1）基本功能：秒、分钟、小时计时、显示及校对； 2）整点报时功能：在每小时59分50秒开始500Hz频率发声提示，整点时1000Hz发声，之后声音停止； 3）定时报闹功能：可设定闹钟定点报闹，可用开
VHDL-music-generator-report-code
- VHDL实现音乐发生器,并进行FPGA验证！报告中含有各模块详细代码，和仿真波形！-VHDL music generator and FPGA verification! The report contains a detailed code of each module, and the simulation waveform!
Codes-and-Reports
- Verilog Source code for arbitrary waveform generator- simple DDS algorithm codes run on Xilinx Spartan-3E fpga to show output on dac pin. Please see the included report. its really simple to implement. all source code is given.
Random-number-generator-verilog
- Verilog code for a pseudo random number generator using linear shift registers. Implemented on Basys2 with Xilinx. Project report also is included.
e12HDB3
- 清华大学电子工程系 HDB3实验报告 包括：M序列发生器，编码器，解码器-Electronic Engineering, Tsinghua University HDB3 lab report include: M sequence generator, encoders, decoders
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of