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signalgenerater
- 一个简单的多种信号的发生器 包括正玄，锯齿，阶梯等，使用时用quartus 4.0以上版本打开-a simple multiple signal generator including Shogen, sawtooth, the ladder, when used with the above version 4.0 Quartus open
mc8051_design
- This is version 1.4 of the MC8051 IP core.
dram
- 4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version.
4Day
- 《4天学会Design Compiler》的中文版。 《4天学会Design Compiler》大家都该知道的，一个很好的DC入门教才，我也是学习时找到了这个中文版。 《4天学会Design Compiler》可以在xunlei上下载到。-" 4-day Institute of Design Compiler" the Chinese version. " 4-day Institute of Design Compiler" Everyone in
cic_intp_64_four
- 4阶CIC内插滤波器，内插系数64，Verilog版本，数字下变频-4-order interpolating CIC filter interpolation factor of 64, Verilog version of the digital down-conversion
jianpanjiekoups2
- 【原创】44矩阵键盘接口程序（VHDL）(2009-10-27 201747) 标签：矩阵键盘vhdl杂谈 初级版：支持输入三个十位数字组成的两个操作数加减与或比较运算，零占位不可省。 程序代码：-【Original】 44 matrix keyboard interface program (VHDL) (2009-10-27 201747) Tags: Matrix keyboard vhdl Zatan junior version: support the i
4weiquanjia
- 用VHDL写的4位全加器,5.1版本编写的-Use VHDL to write four full adder, 5.1 version of the written
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
SPI
- Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous comm
MDB_Version_4-2
- mdb协议，包含各种终端，自动售货机协议-Version 4.1 of this specification is the fifth release of the international Multi-Drop Bus/ Internal Communication Protocol (MDB/ICP).
verilog4
- Learning Verilog Chinese Version Part 4
lab4_project
- lab4中基于ISE的lab4实验的程序源代码，这里使用的是ISE13.4的版本-lab4 in ISE-based lab4 experimental program source code, here is the version ISE13.4
avnet_edk12_4_xbd_files
- 安富利SP605开发板ISE12.4版本的XBD文件，里面包括了开发板所有的接口，包括硬件和软件设计-Avnet SP605 development board ISE12.4 version XBD file, which includes the development board all interfaces, including hardware and software design
hash_function_sha3
- The synthesis software is Xilinx ISE version 14.4. The low throughput core has been synthesized targeting a very cheap Spartan 3 (XC3S5000-4FG900). This project is licensed under the Apache License, version 2. I prefered on the internet
Spartan-6-PCIE_tutorial1
- xilinx Spartan 6 PCIE仿真教程，PIO方式，带有TLP包分析。-XILINX PCIE tutorial device spartan6 PCIE core version V2.4
TwoOderPll
- 1、资料包含二阶环路设计简要说明，Matlab程序，Matlab程序模拟FPGA工作方式，对各变量进行了量化处理 2、资料包含使用Vivado2015.4.2版本的工程文件，可直接运行查看仿真结果 3、参考资料为杜勇老师的《锁相环技术原理及其FPGA实现》(1. The data include a brief descr iption of the second-order loop design. The MATLAB program and the MATLAB program sim