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cycloneIII3c120dev
- This document describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board.-This document describes the ha
EPM7128_flash_config_controller
- Using the Nios Development Board Configuration Controller Reference Designs
Chapter-2
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-3
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-4
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-5
- Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are
Chapter-6
- 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
Chapter-7
- 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are program
Chapter-8
- 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on
DE2_NIOS_HOST_MOUSE_VGA
- 该设计使用了Nios II系统来演示如何在DE2开发板上的USB主机端口连接到一个USB设备进行通信。本设计实现了一个单色显示屏，预加载的图像，用户可以利用它与鼠标。应连接到VGA端口，一个USB鼠标连接到USB主机端口和一个CRT/ LCD显示器。-This designs uses a Nios II system to demonstrate how to communicate with a USB device connected to the USB HOST port on the
DE2_SD_Card_Audio
- 该设计使用了Nios II系统来演示如何从SD卡读取。该软件从SD卡读取WAV文件并播放它通过LINE OUT线。简单地把SD卡插入插槽，在板子上，并连接音箱的LINE OUT端口。-This designs uses a Nios II system to demonstrate how to read from the SD card. The software reads WAV files from the SD card and plays it through the LINE OU
Using_the_SDRAM_on_DE0_Board
- Using the SDRAM on Altera’s DE0 Board with VHDL Designs
DE2_Top
- 此设计是一个裸机的设计，其中包含在DE2开发板所有的引脚分配。它还包含一个与所有的对应于每个引脚的输入/输出端口的Verilog模块。这可以被用来作为一个起点上的电路板的设计。-This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output por
Crossover-design
- 在Altera DE2-70的开发板上实现分频计设计。-In the Altera DE2-70 development board to achieve crossover meter designs.
Z-turn-examples-master
- # Z-turn-examples The repository with my simple Z-turn examples, to be used as templates for more serious projects. Please note, that the Buildroot configuration in my designs sets the root password to "test". Setting the password is n