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vga.niosII.compent.v
- 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
9.16 fifoasi
- 主要完成数字电视前端信号处理和缓冲作用的verilog源代码，可以直接使用 -the major digital TV front-end signal processing and buffer the Verilog source code can be used directly
dual_RAM.rar
- actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码,actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog
fifo
- FIFO 是一种先进先出数据缓存器，这是一个同步FIFO的VHDL源程序，将FIFO分成几个模块进行设计，最后用顶层文件进行模块化设计。-FIFO is a FIFO buffer, which is a synchronous FIFO in VHDL source code, will be divided into several modules FIFO design, top-level files Finally, the modular design.
88fifovhdl
- 88位进出缓冲器8*8位的fifo数据缓冲器的vhdl源程序 编了个8*8位的fifo数据缓冲器的vhdl源程序，是经过quartusII4.2编译成功的程序。。希望能跟各位交流-88 out of 8* 8-bit buffer fifo data buffer vhdl source Bianle Ge 8* 8-bit data buffer fifo vhdl source code is compiled through quartusII4.2 successful progra
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
vga_gui
- 在DE2开发板上实现，由于DE2中的SSRAM只有512K，所以640*480*3（byte）的显存是不够的显示结果是经缩放 后的效果，具体可修改Altera_UP_Avalon_Pixel_Buffer buffer模块中的相关代码。 我把代码移植到DE2-70上后，显示的就很正常了。-In the DE2 development board to achieve, due to the SSRAM DE2 only 512K, so 640* 480* 3 (byte)
auk_rtprx-v3.1.0.tar
- The Altera(R) RTP Receiver function implements a buffer for received RTP packets. Duplicated and re-ordered packets are corrected. Missing packets can be fixed using Pro-MPEG Code of Practice #3 Forward Error Correction
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
FIFO24_CS8416[1]
- Fifo buffer vhdl code
FIFO24_psconv
- fifo buffer vhdl code
FIFO_ise11migration
- fifo buffer vhdl code
atapi_ctl_2_5
- fifo buffer vhdl code
atapi_ctl_2_6
- fifo buffer vhdl code
lab1(mka)
- RGB vga driver for manipulating the colours of a given image buffer. The code has beeen written in vhdl
SPI
- 含有fifo缓冲器的SPI接口源代码，用verilog语言实现-SPI Interface fifo buffer containing the source code, using verilog language
FIFO
- 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Altera_VHDL
- this is vhdl code. and, or, buffer gate code device is altera cyclone2.
FLOATING-BUFFER
- Floating Buffer verilog code for NOC design used for dynamic reconfiguration.