VHDL语言 FPGA 一百进制计数器 元件例化方法-VHDL, FPGA hundred cases of binary counter element method

以Altera公司的MAX+plus II为工具软件，采用Verilog HDL文本输入设计法设计8位二进制加减计数器，生成元件符号-Altera s MAX+plus II tools software, using Verilog HDL text input method to design8 binary addition and subtraction counter, generating element symbol

Including quaternion various calculations, Using a large number of finite element method to solve partial differential equations, Modulated signals to calculate its density Pu-related.