数字均衡器是通讯信道抗码间干扰的重要环节,这是一个用vhdl写的代码以及用SYNPLIFY8.0综合的RTL电路图 它包含三个模块FILTER,ERR_DECISION,ADJUST 希望对大家有用.-equalizer communications channel anti-inter-symbol interference an important link This is a use of the VHDL code to write and use SYNPLIFY8.0 integra

用verilog 语言实现数字通信中最先进的技术之一中的OFDM技术中的添加循环前缀，可以减少码间干扰，并实现符号同步-a great complied code of cyclic prefix for OFDM which is good for intersymbol interference and inter channel interference